AM3874 datasheet(173/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

Table 7-2. Core Logic Voltage Domains and Supply Pin Associations

CORE LOGIC

SUPPLY PIN NAME

VOLTAGE DOMAIN

ARM_L

CVDD_ARM

CORE_L

CVDD

Note: A regulated supply voltage must be supplied to each Core Logic Voltage Domain at all times,

regardless of the Core Logic Power Domain states.

7.2.1.2

Memory Voltage Domains

The SRAM within each Device Module is assigned to one of four Memory Voltage Domains. The voltage

of each Memory Voltage Domain is independently controlled by internal LDO regulators, which are

supplied by the VDDA_1P8 pins.

The voltage level output by each of these LDO regulators is controlled through software by programming

the RAMLDO_CTRLx registers in the Control Module. The Memory Voltage Domain voltage must be

programmed based on the Core Logic Voltage Domain voltage for that domain (that is, the corresponding

Core Logic Voltage Domain for the ARM_M Voltage Domain is ARM_C, and so on). Table 7-3 shows the

Memory Voltage Domain voltage requirements.

Table 7-3. Memory Voltage Domain LDO Requirements

CORE LOGIC VOLTAGE

MEMORY VOLTAGE DOMAIN

DOMAIN VOLTAGE (V)

VOLTAGE (V)

0.83 – 1.20

1.20

7.2.1.3

Power Domains

The device contains six Power Domains which supply power to both the Core Logic and SRAM within their

associated modules. Each Power Domain, except for the ALWAYS ON domain, has an internal power

switch that can completely remove power from that domain. All power switches are turned "OFF" by

default after reset, and software can individually turn them "ON/OFF" via Control Module registers.

Note: All Modules within a Power Domain are unavailable when the domain is powered "OFF". For

instructions on powering "ON/OFF" the Power domains, see the Power, Reset, and Clock Management

(PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature

Number: SPRUGZ7).

7.2.2

SmartReflex [Not Supported]

The device contains SmartReflex modules that help to minimize power consumption on the Core Logic

Voltage Domains by using external variable-voltage power supplies. Based on the device process,

temperature, and desired performance, the SmartReflex modules advise the host processor to raise or

lower the supply voltage to each domain for minimal power consumption.

The communication link between the host processor and the external regulators is a system-level decision

and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly

describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling

(DVFS) and Adaptive Voltage Scaling (AVS).

7.2.2.1

Dynamic Voltage Frequency Scaling (DVFS)

Each device Core Logic Voltage Domain can be run independently at one of several Operating

Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1)

maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage

range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower

voltage ranges for power savings.

Power, Reset, Clocking, and Interrupts

173

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