AM3874 datasheet(184/361 Pages) TI

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AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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7.3.14 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is de-asserted (high) when the device is out

reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In

addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR

and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin

(high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see

Section 4.5.1, Pullup/Pulldown Resistors.

If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT

is also asserted when any of the below resets occur:

•

Power-On Reset (asserted after the BTMODE[11] pin is latched)

•

External Warm Reset (asserted after the BTMODE[11] pin is latched)

•

Emulation Warm Reset

•

Software Global Cold/Warm Reset

The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8

processor for reset.

7.3.15 Effect of Reset on Emulation and Trace

The device Emulation and Trace Logic will only be reset by the following sources:

•

Power-On Reset

•

Software Global Cold Reset

•

Test Reset

Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic.

However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

7.3.16 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is

asserted under either of the following two conditions:

1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs

2. When that Power Domain switches from the "ON" state to the "OFF" state

Cold Reset for a Power Domain is asserted under either of the following two conditions:

1. Power-On Reset or Software Global Cold Reset occurs

2. When that Power Domain switches from the "OFF" state to the "ON" state

7.3.17 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 7.3.1, System-Level Reset Sources) is

asserted, all device I/O pins are reset into a Hi-Z state except for:

•

Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.

•

EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However,

some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the

ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For

more details, see the description of the RESET_ISO register in the Control Module chapter of the

AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

•

RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed

information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

184

Power, Reset, Clocking, and Interrupts

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