AM3874 datasheet(186/361 Pages) TI

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RESET STATE

DEV_CLKIN/

AUX_CLKIN

(A)

POR

RESET

BTMODE[15:0]

Other I/O Pins

(C)

Power

Supplies

Ramping

Power Supplies Stable

Clock Source Stable

Config

Hi-Z

RSTOUT_WD_OUT

BTMODE[11]

(B)

Hi-Z

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

www.ti.com

Table 7-10. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-5) (continued)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

td(PORH-

Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

RSTOUTL)

value(1)(2)

td(RSTH-

Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

RSTOUTD)

value(1)(2)

Figure 7-4 shows the Power-Up Timing. Figure 7-5 shows the Warm Reset (RESET) Timing. Max Reset

Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched.

Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of tw(RESET).

RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.

For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also

see Section 3.2, Terminal Functions for the IPU/IPD settings during reset.

Figure 7-4. Power-Up Timing

186

Power, Reset, Clocking, and Interrupts

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