AM3874 datasheet(185/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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DDR[0]/[1] Address/Control Pins (CLK, CLK, CKE, WE, CS[1]/[0], RAS, CAS, ODT[1]/[0], RST,

BA[2:0], A[14:0]). These pins are 3-stated during reset. However, these pins are then driven to the

same value as their internal pull resistor reset value when reset is released (For the direction of the

internal pull during reset, see the DDR[0]/[1] Terminal Functions tables in the Section 3.2.4,

DDR2/DDR3 Memory Controller of this document).

In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling

the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents

some PINCNTL registers from being reset.

For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the

PINCNTL registers in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical

Reference Manual (Literature Number: SPRUGZ7).

Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in

Section 3.2, Terminal Functions of this document.

NOTE

Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot

ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated

pins for the chosen primary and backup Bootmodes. For more details on the Boot ROM

effects on pin multiplexing, see the ROM Code Memory and Peripheral Booting and Control

Module chapters of the AM387x Sitara™ ARM Processors Technical Reference Manual

(Literature Number: SPRUGZ7).

7.3.18 Reset Electrical Data/Timing

Table 7-9. Timing Requirements for Reset (see Figure 7-4 and Figure 7-5)

OPP100

NO.

UNIT

MIN

MAX

tw(RESET)

Pulse duration, POR low or RESET low

12P(1)

POR

2P(2)

Setup time, BTMODE[15:0] pins valid before POR high or

tsu(BOOT)

RESET high

RESET

2P(2)

th(BOOT)

Hold time, BTMODE[15:0] pins valid after POR high or RESET high

(1)

The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.

(2)

P = 1/(DEV Clock) frequency in ns.

Table 7-10. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-5)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

td(RSTL-

Delay time, RESET low or POR low to all I/Os entering their reset state

IORST)

td(RSTH-

Delay time, RESET high or POR high to all I/Os exiting their reset state

IOFUNC)

RESET assertion tw(RESET)

≥ 30P

td(RSTH-

Delay time, RESET high to RSTOUT_WD_OUT high(1)(2)

RSTOUTH)

RESET assertion tw(RESET)

32P -

< 30P

tw(RESET)

td(PORH-

Delay time, POR high to RSTOUT_WD_OUT high(1)(2)

12500P

RSTOUTH)

td(RSTL-

Delay time, RESET low to RSTOUT_WD_OUT Hi-Z(1)(2)

RSTOUTZ)

(1)

For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

(2)

P = 1/(DEV Clock) frequency in ns.

Power, Reset, Clocking, and Interrupts

185

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