AM3874 datasheet(194/361 Pages) TI

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0111

0110

0100

0101

1011-1111

1010

1000

1001

0011

CLKOUT_MUX

CLKOUT0

RESERVED

RCOSC32K Output

PLL_SGX Output

DEV_OSC Clock Input

AUX Clock

DEV Clock

PLL_L3 Output

PLL_MEDIACTL Output / 2

PLL_DSS Output / 2

0001

0010

0000

(A)

PCIE SERDES Observation Clock

SATA SERDES Observation Clock

PRCM SYSCLK Output

CLKOUT1

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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Muxed output of DEVOSC clock, USBPLL clock output, VIDEO0 PLL Clock output, and RTC DIVIDER output.

Figure 7-11. CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 7-19.

7.4.7

Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the

device and the external clock oscillator circuit.

Table 7-15. Timing Requirements for DEVOSC_MXI/DEV_CLKIN(1) (2) (3)(see Figure 7-12)

OPP100

UNIT

MIN

NOM

MAX

tc(DMXI)

Cycle time, DEVOSC_MXI/DEV_CLKIN

33.33

tw(DMXIH)

Pulse duration, DEVOSC_MXI/DEV_CLKIN high

0.45C

0.55C

tw(DMXIL)

Pulse duration, DEVOSC_MXI/DEV_CLKIN low

0.45C

0.55C

tt(DMXI)

Transition time, DEVOSC_MXI/DEV_CLKIN

tJ(DMXI)

Period jitter, DEVOSC_MXI/DEV_CLKIN

0.02C

If Ethernet not used

±200

Frequency Stability

If MII is used and RGMII, RMII not used

±100

ppm

If RGMII, or RMII used

±50

(1)

The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are

within the specific ranges shown in the Section 7.4.9, SYSCLKs and Section 7.4.10, Module Clocks.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(3)

C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.

194

Power, Reset, Clocking, and Interrupts

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