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AM3874 Datasheet(PDF) 203 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 203 Page - Texas Instruments |
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203 / 361 page  AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 7.4.10 Module Clocks Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 7-27 lists the clock source options for each Module on this device, along with the maximum frequency that Module can accept. To ensure proper Module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table. Table 7-27. Maximum Module Clock Frequencies(1) MAX FREQUENCY MODULE CLOCK SOURCES OPP100 (MHz) PLL_ARM Cortex-A8 600 SYSCLK18 DCAN0/1 DEV Clock 30 DDR0/1 PLL_DDR 400 DMM PLL_DDR/2 200 EDMA SYSCLK4 200 EMAC Switch (GMII) SATA SERDES Fixed 125 PLL_VIDEO0 PLL_VIDEO1 EMAC Switch (RGMII) Fixed 250 PLL_VIDEO02 PLL_L3 SATA SERDES EMAC Switch (RMII and MII) Fixed 50 EMAC_RMREFCLK Pin GPIO SYSCLK6 100 GPIO Debounce SYSCLK18 Fixed 0.032768 GPMC SYSCLK6 100 HDMI PLL_VIDEO2 186 HDMI CEC SYSCLK10 Fixed 48 SYSCLK20 SYSCLK21 HDMI I2S 50 AUD_CLK0/1/2 AUX Clock HDVPSS PLL_HDVPSS 200 PLL_VIDEO2 HDVPSS VOUT1 186 HDMI PHY PLL_VIDEO1 HDVPSS VOUT0 165 PLL_VIDEO2 HDVPSS SD VENC PLL_VIDEO0 Fixed 54 I2C0/1/2/3 SYSCLK10 48 ISS PLL_ MEDIACTL 400 L3 Fast SYSCLK4 200 L3 Medium SYSCLK4 200 L3 Slow SYSCLK6 100 L4 Fast SYSCLK4 200 L4 Slow SYSCLK6 100 Mailbox SYSCLK6 100 McASP SYSCLK6 100 SYSCLK20 McASP0/1/2 AUX_CLK 192 SYSCLK21 PLL_AUDIO PLL_VIDEO0/1/2 McASP3/4/5 AUX_CLK 192 AUD_CLK0/1/2 AUX Clock (1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have higher maximum values when OPP120 or OPP166 is used, see Table 7-4 Copyright © 2011–2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 203 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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