AM3874 datasheet(267/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

8.11 Inter-Integrated Circuit (I2C)

The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices

compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External

components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through

the I2C module. The I2C port does not support CBUS compatible devices.

The I2C port supports the following features:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

•

Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)

•

Noise filter to remove noise 50 ns or less

•

Seven- and ten-bit device addressing modes

•

Multimaster transmitter/slave receiver mode

•

Multimaster receiver/slave transmitter mode

•

Combined master transmit/receive and receive/transmit modes

•

Two DMA channels, one interrupt line

•

Built-in FIFO (32 byte) for buffered read or write.

For more detailed information on the I2C peripheral, see the Inter-Integrated Circuit (I2C) Controller

Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature

Number: SPRUGZ7).

8.11.1 I2C Peripheral Register Descriptions

Table 8-45. I2C Registers

HEX ADDRESS

I2C0

I2C1

I2C2

I2C3

ACRONYM

0x4802 8000

0x4802 A000

0x4819 C000

0x4819 E000

I2C_REVNB_LO

Module Revision (LOW BYTES)

0x4802 8004

0x4802 A004

0x4819 C004

0x4819 E004

I2C_REVNB_HI

Module Revision (HIGH BYTES)

0x4802 8010

0x4802 A010

0x4819 C010

0x4819 E010

I2C_SYSC

System configuration

0x4802 8020

0x4802 A020

0x4819 C020

0x4819 E020

I2C_EOI

I2C End of Interrupt

0x4802 8024

0x4802 A024

0x4819 C024

0x4819 E024

I2C_IRQSTATUS_RA

I2C Status Raw

0x4802 8028

0x4802 A028

0x4819 C028

0x4819 E028

I2C_IRQSTATUS

I2C Status

0x4802 802C

0x4802 A02C

0x4819 C02C

0x4819 E02C

I2C_IRQENABLE_SET

I2C Interrupt Enable Set

0x4802 8030

0x4802 A030

0x4819 C030

0x4819 E030

I2C_IRQENABLE_CLR

I2C Interrupt Enable Clear

0x4802 8034

0x4802 A034

0x4819 C034

0x4819 E034

I2C_WE

I2C Wakeup Enable

0x4802 8038

0x4802 A038

0x4819 C038

0x4819 E038

I2C_DMARXENABLE_

Receive DMA Enable Set

SET

0x4802 803C

0x4802 A03C

0x4819 C03C

0x4819 E03C

I2C_DMATXENABLE_

Transmit DMA Enable Set

SET

0x4802 8040

0x4802 A040

0x4819 C040

0x4819 E040

I2C_DMARXENABLE_

Receive DMA Enable Clear

CLR

0x4802 8044

0x4802 A044

0x4819 C044

0x4819 E044

I2C_DMATXENABLE_

Transmit DMA Enable Clear

CLR

0x4802 8048

0x4802 A048

0x4819 C048

0x4819 E048

I2C_DMARXWAKE_EN Receive DMA Wakeup

0x4802 804C

0x4802 A04C

0x4819 C04C

0x4819 E04C

I2C_DMATXWAKE_EN Transmit DMA Wakeup

0x4802 8090

0x4802 A090

0x4819 C090

0x4819 E090

I2C_SYSS

System Status

0x4802 8094

0x4802 A094

0x4819 C094

0x4819 E094

I2C_BUF

Buffer Configuration

0x4802 8098

0x4802 A098

0x4819 C098

0x4819 E098

I2C_CNT

Data Counter

0x4802 809C

0x4802 A09C

0x4819 C09C

0x4819 E09C

I2C_DATA

Data Access

0x4802 80A4

0x4802 A0A4

0x4819 C0A4

0x4819 E0A4

I2C_CON

I2C Configuration

0x4802 80A8

0x4802 A0A8

0x4819 C0A8

0x4819 E0A8

I2C_OA

I2C Own Address

Peripheral Information and Timings

267

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