AM3874 datasheet(297/361 Pages) TI

297 / 361 page

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

8.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias

If a power plane is used as a reference plane then additional bypass capacitors may be required to

accommodate the signal return currents. Care should be taken to minimize the layer transitions during

routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane.

If this cannot be accommodated, ensure there is a nearby path to allow the return currents to transition

between reference planes. Transitions from power reference planes to ground reference planes must go

through a bypass capacitor. Transition between different ground references or DVDD_DDR planes can go

through a connecting via. As many of these return current bypass capacitors or vias should be used as

possible. The goal is to minimize the size of the return current loops. Generally, this type of situation

happens where signals must transition from horizontal to vertical routing and vice-versa.

8.13.4.2.4.7 Net Classes

Table 8-73 lists the clock net classes for the DDR3 interface. Table 8-74 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-73. Clock Net Class Definitions

CLOCK NET CLASS

PROCESSOR PIN NAMES

DDR[x]_CLK/DDR[x]_CLK

DQS0

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DQS1

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DQS2(1)

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DQS3(1)

DDR[x]_DQS[3]/DDR[x]_DQS[3]

(1)

Only used on 32-bit wide DDR3 memory systems.

Table 8-74. Signal Net Class Definitions

ASSOCIATED CLOCK

CLOCK NET CLASS

PROCESSOR PIN NAMES

NET CLASS

ADDR_CTRL

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE, DDR[x]_ODT[x]

DQ0

DQS0

DDR[x]_D[7:0], DDR[x]_DQM[0]

DQ1

DQS1

DDR[x]_D[15:8], DDR[x]_DQM[1]

DQ2(1)

DQS2

DDR[x]_D[23:16], DDR[x]_DQM[2]

DQ3(1)

DQS3

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1)

Only used on 32-bit wide DDR3 memory systems.

8.13.4.2.4.8 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.13.4.2.4.9 VREFSSTL_DDR Routing

VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as

the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with

the DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF

bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing

congestion.

Peripheral Information and Timings

297

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