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AM3874 Datasheet(PDF) 293 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 293 Page - Texas Instruments

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AM3874, AM3871
www.ti.com
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
8.13.4.2.4.1 Compatible JEDEC DDR3 Devices
Table 8-66 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1600 devices in the x8 or x16 widths.
Table 8-66. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
MIN
MAX
UNIT
1
JEDEC DDR3 device speed grade(1)
DDR3-800
DDR3-
1600(2)
2
JEDEC DDR3 device bit width
x8
x16
Bits
3
JEDEC DDR3 device count(3)
2
8
Devices
(1)
DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.
(2)
DDR3 devices with speed grades up to DDR3-1600 are supported; however, max clock rate will still be limited to 533 MHz as stated in
Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.
(3)
For valid DDR3 device configurations and device counts, see Section 8.13.4.2.4, Figure 8-54, and Figure 8-55.
8.13.4.2.4.2 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-67.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-68.
Complete stackup specifications are provided in Table 8-69.
Table 8-67. Minimum PCB Stackup
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Split power plane
3
Plane
Full ground plane
4
Signal
Bottom routing mostly horizontal
Table 8-68. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Ground
3
Plane
Split power plane
4
Plane
Split power plane or Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly horizontal
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
293
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Product Folder Links: AM3874 AM3871



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