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PEB2256HT Datasheet(PDF) 370 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 370 Page - Infineon Technologies AG |
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370 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 370 2002-08-27 ELT Enable Loop-Timed 0 = Normal operation 1 = Transmit clock is generated from the clock supplied by MCLK which is synchronized to the extracted receive route clock. In this configuration the transmit elastic buffer has to be enabled. Refer to register FMR5.XTM. For correct operation of loop timed the remote loop (bit LIM1.RL = 0) must be inactive and bit CMR1.DXSS must be cleared. LOS1 Loss-of-Signal Recovery condition 0 = The LOS alarm is cleared if the predefined pulse-density (register PCR) is detected during the time interval which is defined by register PCD. 1 = Additionally to the recovery condition described above a LOS alarm is only cleared if the pulse-density is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval (according to GR-499-CORE). Loop Code Register 1 (Read/Write) Value after reset: 00 H EPRM Enable Pseudo-Random Binary Sequence Monitor 0 = Pseudo-random binary sequence (PRBS) monitor is disabled. 1 = PRBS is enabled. Setting this bit enables incrementing the bit error counter BEC with each detected PRBS bit error. With any change of state of the PRBS internal synchronization status an interrupt ISR3.LLBSC is generated. The current status of the PRBS synchronizer is indicated by bit FRS1.LLBAD. XPRBS Transmit Pseudo-Random Binary Sequence A one in this bit position enables transmission of a pseudo-random binary sequence to the remote end. Depending on bit LLBP the PRBS is generated according to 2 15 -1 or 220-1 (ITU-T O. 151). 70 LCR1 EPRM XPRBS LDC1 LDC0 LAC1 LAC0 FLLB LLBP (3B) |
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