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PEB2256HT Datasheet(PDF) 373 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 373 Page - Infineon Technologies AG |
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373 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 373 2002-08-27 System Interface Control 1 (Read/Write) Value after reset: 00H SSC(1:0) Select System Clock SIC1.SSC(1:0) and SIC2.SSC2 define the clocking rate on the system highway. SIC2.SSC2 = 0: 00 = 2.048 MHz 01 = 4.096 MHz 10 = 8.192 MHz 11 = 16.384 MHz SIC2.SSC2 = 1: 00 = 1.544 MHz 01 = 3.088 MHz 10 = 6.176 MHz 11 = 12.352 MHz SSD1 Select System Data Rate 1 SIC1.SSD1, FMR1.SSD0 and SIC2.SSC2 define the data rate on the system highway. Programming SSD1/SSD0 and corresponding data rate is shown below. SIC2.SSC2 = 0: 00 = 2.048 Mbit/s 01 = 4.096 Mbit/s 10 = 8.192 Mbit/s 11 = 16.384 Mbit/s SIC2 .SSC2 = 1: 00 =1.544 Mbit/s 01 = 3.088 Mbit/s 10 = 6.176 Mbit/s 11 = 12.352 Mbit/s 70 SIC1 SSC1 SSD1 RBS1 RBS0 SSC0 BIM XBS1 XBS0 (3E) |
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