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PEB2256HT Datasheet(PDF) 372 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 372 Page - Infineon Technologies AG |
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372 / 490 page ![]() FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 372 2002-08-27 Loop Code Register 2 (Read/Write) Value after reset: 00 H LDC(7:0) Line Loop-Back Deactivate Code If enabled by bit FMR5.XLD = 1 the LLB deactivate code automatically repeats until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LDC0 is transmitted last. For correct operations bit LCR1.XPRBS has to cleared. If LCR2 is changed while the previous deactivate code has been detected and is still received, bit FRS1.LLBDD will stay active until the incoming signal changes or a receiver reset is initiated (CMDR.RRES = 1). Loop Code Register 3 (Read/Write) Value after reset: 00 H LAC(7:0) Line Loop-Back Activate Code If enabled by bit FMR5.XLU = 1 the LLB activate code automatically repeats until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LAC0 is transmitted last. For correct operations bit LCR1.XPRBS has to cleared. If LCR3 is changed while the previous activate code has been detected and is still received, bit FRS1.LLBAD will stay active until the incoming signal changes or a receiver reset is initiated (CMDR.RRES = 1). 70 LCR2 LDC7 LDC0 (3C) 70 LCR3 LAC7 LAC0 (3D) |
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