MSP430F5259IRGCT datasheet(35/112 Pages) TI1

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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

5.35 USCI (UART Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK, ACLK

fUSCI

USCI input clock frequency

External: UCLK

fSYSTEM

MHz

Duty cycle = 50% ±10%

BITCLK clock frequency

fBITCLK

MHz

(equals baud rate in MBaud)

5.36 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VCC

VIO

MIN

MAX

UNIT

1.8 V

1.62 V to 1.80 V

600

tτ

UART receive deglitch time(1)

3.0 V

1.62 V to 1.98 V

600

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.37 USCI (SPI Master Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

fUSCI

USCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ±10%

5.38 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

(see Figure 5-13 and Figure 5-14)

PARAMETER

TEST CONDITIONS

VCC

VIO

MIN

MAX

UNIT

SMCLK or ACLK,

fUSCI

USCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ±10%

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tSU,MI

SOMI input data setup time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tHD,MI

SOMI input data hold time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

UCLK edge to SIMO valid,

CL = 20 pF, PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tVALID,MO

SIMO output data valid time(2)

2.4 V

1.62 V to 1.98 V

UCLK edge to SIMO valid,

CL = 20 pF, PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

–10

CL = 20 pF, PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

–10

tHD,MO

SIMO output data hold time(3)

2.4 V

1.62 V to 1.98 V

–10

CL = 20 pF, PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

–10

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-13 and Figure 5-14.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

13 and Figure 5-14.

Specifications

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MSP430F5259IRGCT Datasheet(PDF) 35 Page - Texas Instruments

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