MSP430F5259IRGCT datasheet(11/112 Pages) TI1

11 / 112 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

www.ti.com

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

Table 4-1. Terminal Functions (continued)

TERMINAL

NO.(2)

I/O(1)

SUPPLY

DESCRIPTION

NAME

RGC

ZQE

General-purpose digital I/O with port interrupt

Slave transmit enable – USCI_B3 SPI mode

P2.5/UCB3STE/UCA3CLK(5)

I/O

DVIO

Clock signal input – USCI_A3 SPI slave mode

Clock signal output – USCI_A3 SPI master mode

General-purpose digital I/O with port interrupt

P2.6/RTCCLK/DMAE0(5)

I/O

DVIO

RTC clock output for calibration

DMA external trigger input

General-purpose digital I/O

Slave transmit enable – USCI_B0 SPI mode

P2.7/UCB0STE/UCA0CLK(5)

I/O

DVIO

Clock signal input – USCI_A0 SPI slave mode

Clock signal output – USCI_A0 SPI master mode

General-purpose digital I/O

P3.0/UCB0SIMO/UCB0SDA(5)

I/O

DVIO

Slave in, master out – USCI_B0 SPI mode

I2C data – USCI_B0 I2C mode

General-purpose digital I/O

P3.1/UCB0SOMI/UCB0SCL(5)

I/O

DVIO

Slave out, master in – USCI_B0 SPI mode

I2C clock – USCI_B0 I2C mode

General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode

P3.2/UCB0CLK/UCA0STE(5)

I/O

DVIO

Clock signal output – USCI_B0 SPI master mode

Slave transmit enable – USCI_A0 SPI mode

General-purpose digital I/O

P3.3/UCA0TXD/UCA0SIMO (5)

I/O

DVIO

Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode

General-purpose digital I/O

P3.4/UCA0RXD/UCA0SOMI (5)

I/O

DVIO

Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode

DVSS

Digital ground supply

DVIO(6)

Digital I/O power supply

General-purpose digital I/O with reconfigurable port mapping

secondary function

Default mapping: Slave transmit enable – USCI_B1 SPI mode

P4.0/PM_UCB1STE/

I/O

DVIO

Default mapping: Clock signal input – USCI_A1 SPI slave

PM_UCA1CLK(5)

mode

Default mapping: Clock signal output – USCI_A1 SPI master

mode

General-purpose digital I/O with reconfigurable port mapping

secondary function

P4.1/PM_UCB1SIMO/

I/O

DVIO

PM_UCB1SDA(5)

Default mapping: Slave in, master out – USCI_B1 SPI mode

Default mapping: I2C data – USCI_B1 I2C mode

General-purpose digital I/O with reconfigurable port mapping

secondary function

P4.2/PM_UCB1SOMI/

I/O

DVIO

PM_UCB1SCL(5)

Default mapping: Slave out, master in – USCI_B1 SPI mode

Default mapping: I2C clock – USCI_B1 I2C mode

(6)

The voltage on DVIO is not supervised or monitored.

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254

MSP430F5253 MSP430F5252

MSP430F5259IRGCT Datasheet(PDF) 11 Page - Texas Instruments

MSP430F5259IRGCT Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL