MSP430F5259IRGCT datasheet(48/112 Pages) TI1

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

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6.3

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-1. Interrupt Sources, Flags, and Vectors

SYSTEM

WORD

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

INTERRUPT

ADDRESS

System Reset

Power-Up

External Reset

Watchdog Timeout, Password

WDTIFG, KEYV (SYSRSTIV)(1) (2)

Reset

0FFFEh

63, highest

Violation

Flash Memory Password Violation

PMM Password Violation

System NMI

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

PMM

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

(Non)maskable

0FFFCh

Vacant Memory Access

JMBOUTIFG (SYSSNIV) (1)

JTAG Mailbox

User NMI

NMI

NMIIFG, OFIFG, ACCVIFG, BUSIFG

(Non)maskable

0FFFAh

Oscillator Fault

(SYSUNIV)(1) (2)

Flash Memory Access Violation

COMP_B

Comparator B interrupt flags (CBIV) (1) (3)

Maskable

0FFF8h

USCI_A0 Receive or Transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3)

Maskable

0FFF6h

USCI_B0 Receive or Transmit

UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3)

Maskable

0FFF4h

Watchdog Timer_A Interval Timer

WDTIFG

Maskable

0FFF2h

Mode

USCI_A1 Receive or Transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3)

Maskable

0FFF0h

USCI_B1 Receive or Transmit

UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3)

Maskable

0FFEEh

ADC10_A

ADC10IFG0(1) (3) (4)

Maskable

0FFECh

USCI_A2 Receive or Transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (3)

Maskable

0FFEAh

USCI_B2 Receive or Transmit

UCB2RXIFG, UCB2TXIFG (UCB2IV) (1) (3)

Maskable

0FFE8h

TA0

TA0CCR0 CCIFG0(3)

Maskable

0FFE6h

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0

Maskable

0FFE4h

TA0IFG (TA0IV)(1) (3)

Reserved

Reserved(5)

Maskable

0FFE2h

DMA

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (3)

Maskable

0FFE0h

USCI_A3 Receive or Transmit

UCA3RXIFG, UCA3TXIFG (UCA3IV) (1) (3)

Maskable

0FFDEh

USCI_B3 Receive or Transmit

UCB3RXIFG, UCB3TXIFG (UCB3IV) (1) (3)

Maskable

0FFDCh

TB0

TB0CCR0 CCIFG0 (3)

Maskable

0FFDAh

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0

Maskable

0FFD8h

TB0IFG (TB0IV)(1) (3)

TA1

TA1CCR0 CCIFG0(3)

Maskable

0FFD6h

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1

Maskable

0FFD4h

TA1IFG (TA1IV)(1) (3)

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV) (1) (3)

Maskable

0FFD2h

TA2

TA2CCR0 CCIFG0(3)

Maskable

0FFD0h

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2

Maskable

0FFCEh

TA2IFG (TA2IV)(1) (3)

I/O Port P2

P2IFG.0 to P2IFG.7 (P2IV) (1) (3)

Maskable

0FFCCh

(1)

Multiple source flags

(2)

A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3)

Interrupt flags are in the module.

(4)

Only on devices with ADC, otherwise reserved

(5)

Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, TI recommends reserving these locations.

Detailed Description

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