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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

Table 6-3. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

RST/NMI

External reset

BSLEN

Enable BSL

P4.1/PM_UCB1SDA

I2C data

P4.2/ PM_UCB1SCL

I2C clock

DVCC, AVCC

Device power supply

DVIO

I/O power supply

DVSS

Ground supply

6.5.2

Bootloader – UART

The UART BSL enables users to program the flash memory or RAM using a UART serial interface.

Access to the device memory through the BSL is protected by an user-defined password. Because the

F525x have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO

supply domains. This is useful when the MSP430 is interfacing to a host on the DVIO supply domain. The

BSL interface on the DVIO supply domain (Table 6-5) uses the USCI_A0 module configured as a UART.

The BSL interface on the DVCC supply domain (Table 6-4) uses a timer-based UART.

For applications in which it is desirable to have BSL communication based on the DVCC supply domain,

entry to the BSL requires a specific sequence on the RSTDVCC/SBWTDIO and TEST/SBWTCK pins.

Table 6-4 lists the required pins and their function.

NOTE

Devices that are factory programmed with an UART BSL use the DVCC power supply

domain pin configuration per default (see Table 6-4).

NOTE

To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO pin and

TEST/SBWTCK pin must be used for the entry sequence. It is critical not to confuse the

RST/NMI pin with the RSTDVCC/SBWTDIO pin. In many other MSP430 devices, SBWTDIO

is shared with the RST/NMI pin, and RSTDVCC does not exist. Additional information can be

found in Designing With MSP430F522x and MSP430F521x Devices (SLAA558).

Table 6-4. DVCC BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

RSTDVCC/SBWTDIO

External reset

TEST/SBWTCK

Enable BSL

P6.1

Data transmit

P6.2

Data receive

DVCC, AVCC

Device power supply

DVIO

I/O power supply

DVSS

Ground supply

When using the DVIO supply domain for the BSL, entry to the BSL requires a specific sequence on the

RST/NMI and BSLEN pins. Table 6-5 lists the required pins and their functions. For further details on

interfacing to development tools and device programmers, see the MSP430™ Hardware Tools User's

Guide (SLAU278). For a complete description of the features of the BSL and its implementation, see the

MSP430 Programming With the Bootloader User's Guide (SLAU319). The BSL on the DVIO supply

domain uses the USCI_A0 module configured as a UART.

Detailed Description

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MSP430F5259IRGCT Datasheet(PDF) 51 Page - Texas Instruments

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