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MSP430F5259IRGCT Datasheet(PDF) 87 Page - Texas Instruments |
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MSP430F5259IRGCT Datasheet(HTML) 87 Page - Texas Instruments |
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87 / 112 page ![]() P5.5/XOUT 1 0 P5DIR.5 P5IN.5 EN Module X IN 1 0 Module X OUT P5OUT.5 1 0 DV SS DV CC P5REN.5 Pad Logic 1 P5DS.5 0: Low drive 1: High drive D Bus Keeper to XT1 P5SEL.4 XT1BYPASS P5SEL.5 MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 www.ti.com SLAS903B – MAY 2013 – REVISED NOVEMBER 2015 Table 6-55. Port P5 (P5.4 and P5.5) Pin Functions CONTROL BITS AND SIGNALS(1) PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS P5.4/XIN 4 P5.4 (I/O) I: 0; O: 1 0 X X XIN crystal mode(2) X 1 X 0 XIN bypass mode(2) X 1 X 1 P5.5/XOUT 5 P5.5 (I/O) I: 0; O: 1 0 0 X XOUT crystal mode(3) X 1 X 0 P5.5 (I/O)(3) X 1 0 1 (1) X = Don't care (2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal mode or bypass mode. (3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as general-purpose I/O. Copyright © 2013–2015, Texas Instruments Incorporated Detailed Description 87 Submit Documentation Feedback Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254 MSP430F5253 MSP430F5252 |
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