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MSP430F5259IRGCT Datasheet(PDF) 6 Page - Texas Instruments |
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MSP430F5259IRGCT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 112 page ![]() MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 SLAS903B – MAY 2013 – REVISED NOVEMBER 2015 www.ti.com 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Family Members(1)(2) USCI ADC10 COMP CHANNEL CHANNEL FLASH SRAM I/O I/O BSL DEVICE Timer_A(3) Timer_B(4) _A _B PACKAGE A: B: (KB) (KB) DVCC(5) DVIO(6) TYPE (Ch) (Ch) UART, SPI, I2C IrDA, SPI 10 ext, 64 RGC MSP430F5259 128 32 5, 3, 3 7 4 4 8 18 35 I2C 2 int 80 ZQE 64 RGC MSP430F5258 128 32 5, 3, 3 7 4 4 N/A 8 18 35 I2C 80 ZQE 10 ext, 64 RGC MSP430F5257 128 16 5, 3, 3 7 4 4 8 18 35 I2C 2 int 80 ZQE 64 RGC MSP430F5256 128 16 5, 3, 3 7 4 4 N/A 8 18 35 I2C 80 ZQE 10 ext, 64 RGC MSP430F5255 128 32 5, 3, 3 7 4 4 8 18 35 UART 2 int 80 ZQE 64 RGC MSP430F5254 128 32 5, 3, 3 7 4 4 N/A 8 18 35 UART 80 ZQE 10 ext, 64 RGC MSP430F5253 128 16 5, 3, 3 7 4 4 8 18 35 UART 2 int 80 ZQE 64 RGC MSP430F5252 128 16 5, 3, 3 7 4 4 N/A 8 18 35 UART 80 ZQE (1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. (3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. (4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. (5) All of these I/O reside on a single voltage rail supplied by DVCC. (6) All of these I/O reside on a single voltage rail supplied by DVIO. 6 Device Comparison Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254 MSP430F5253 MSP430F5252 |
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