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MSP430F5259IRGCT Datasheet(PDF) 5 Page - Texas Instruments |
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MSP430F5259IRGCT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 112 page  MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 www.ti.com SLAS903B – MAY 2013 – REVISED NOVEMBER 2015 7.6 Electrostatic Discharge Caution ..................... 99 7.8 Glossary ............................................. 99 7.7 Export Control Notice ............................... 99 8 Mechanical, Packaging, and Orderable Information .............................................. 99 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2013) to Revision B Page • Document format and organization changes throughout, including addition of section numbering ........................ 1 • Added Device Information table .................................................................................................... 2 • Moved Section 1.4, Functional Block Diagram ................................................................................... 3 • Added 16KB RAM option in Figure 1-1, Functional Block Diagram ............................................................ 3 • Added Section 3, Device Comparison, and moved Table 3-1, Family Members, to it ...................................... 6 • Added Section 4, Terminal Configuration and Functions, and moved pinout drawings and terminal functions table to it .............................................................................................................................. 7 • Added indication of terminals powered by DVIO in RGC pinout ............................................................... 7 • Added indication of terminals powered by DVIO in ZQE pinout ............................................................... 8 • Removed preview YFF pinout ....................................................................................................... 8 • Added SUPPLY column and removed YFF column in Table 4-1, Terminal Functions ...................................... 9 • Added Section 5 and moved all electrical specifications to it ................................................................. 14 • Added Section 5.2, ESD Ratings .................................................................................................. 14 • Added note on CVCORE .............................................................................................................. 14 • Added second note "Under certain condtions during the rising transition..." on Figure 5-1 ............................... 15 • Added Section 5.6, Thermal Characteristics .................................................................................... 19 • Moved note on RPull from Section 5.7 to Section 5.8 ........................................................................... 20 • Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 26 • Corrected Test Conditions (removed VREF–) for all parameters in Section 5.43 ........................................... 41 • Updated Test Conditions for all parameters in Section 5.43, 10-Bit ADC, Linearity Parameters: changed from "CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)".......................................................................................................... 41 • Added "CVeREF+ = 20 pF" to EI Test Conditions.................................................................................. 41 • Added "ADC10SREFx = 11b" to Test Conditions for EG and ET.............................................................. 41 • Corrected Test Conditions (removed VREF–) for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters in Section 5.44 .... 41 • Changed MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V .............. 42 • Corrected spelling of MRG bits in fMCLK,MRG parameter symbol and description ............................................ 44 • Throughout document, changed "bootstrap loader" to "bootloader" ......................................................... 50 • Added note to clarify that all JTAG pins are on DVCC ......................................................................... 52 • Added note to indicate that all SBW pins are on DVCC ...................................................................... 53 • Removed YFF package information from Table 6-12, TA0 Signal Connections ............................................ 60 • Removed YFF package information from Table 6-13, TA1 Signal Connections ............................................ 61 • Removed YFF package information from Table 6-14, TA2 Signal Connections ............................................ 62 • Removed YFF package information from Table 6-15, TB0 Signal Connections ............................................ 63 • Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates) ......................... 85 • Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows .................................................................. 85 • Changed P5.5 schematic (added P5SEL.5 input and OR gate) .............................................................. 87 • Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows .................................................................. 87 • Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature, Trademarks, and Electrostatic Discharge Caution sections to it .............................................................. 95 • Added Section 8 .................................................................................................................... 99 Copyright © 2013–2015, Texas Instruments Incorporated Revision History 5 Submit Documentation Feedback Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254 MSP430F5253 MSP430F5252 |
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