MSP430F5259IRGCT datasheet(10/112 Pages) TI1

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

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Table 4-1. Terminal Functions (continued)

TERMINAL

NO.(2)

I/O(1)

SUPPLY

DESCRIPTION

NAME

RGC

ZQE

General-purpose digital I/O

P5.4/XIN

I/O

DVCC

Input terminal for crystal oscillator XT1(3)

General-purpose digital I/O

P5.5/XOUT

I/O

DVCC

Output terminal of crystal oscillator XT1

AVSS

Analog ground supply

DVCC

Digital power supply

DVSS

Digital ground supply

Regulated core power supply output (internal use only, no

VCORE(4)

DVCC

external current loading)

General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK(5)

I/O

DVIO

TA0 clock signal TA0CLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

P1.1/TA0.0(5)

I/O

DVIO

TA0 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P1.2/TA0.1(5)

I/O

DVIO

TA0 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt

P1.3/TA0.2(5)

I/O

DVIO

TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P1.4/TA0.3(5)

I/O

DVIO

TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

P1.5/TA0.4(5)

I/O

DVIO

TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt

P1.6/TA1CLK/CBOUT (5)

I/O

DVIO

TA1 clock signal TA1CLK input

Comparator_B output

General-purpose digital I/O with port interrupt

P1.7/TA1.0(5)

I/O

DVIO

TA1 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P2.0/TA1.1(5)

I/O

DVIO

TA1 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt

P2.1/TA1.2(5)

I/O

DVIO

TA1 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P2.2/UCB3SIMO/UCB3SDA(5)

I/O

DVIO

Slave in, master out – USCI_B3 SPI mode

I2C data – USCI_B3 I2C mode

General-purpose digital I/O with port interrupt

Clock signal input – USCI_B3 SPI slave mode

P2.3/UCB3SOMI/UCB3SCL(5)

I/O

DVIO

Clock signal output – USCI_B3 SPI master mode

Slave transmit enable – USCI_A3 SPI mode

General-purpose digital I/O with port interrupt

Clock signal input – USCI_B3 SPI slave mode

P2.4/UCB3CLK/UCA3STE(5)

I/O

DVIO

Clock signal output – USCI_B3 SPI master mode

Slave transmit enable – USCI_A3 SPI mode

(3)

When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to

DVCC or DVSS to DVIO. In this case, the pin must be configured properly for the intended input swing.

(4)

VCORE is for internal use only. No external current loading is possible. VCORE should be connected only to the recommended

capacitor value, CVCORE (see Section 5.3).

(5)

This pin function is supplied by DVIO. See Section 5.8 for input and output requirements.

Terminal Configuration and Functions

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