MSP430F5259IRGCT datasheet(14/112 Pages) TI1

14 / 112 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

www.ti.com

Specifications

5.1

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Voltage applied at VCC to VSS

–0.3

4.1

Voltage applied at VIO to VSS

–0.3

2.2

Voltage applied to any pin (excluding VCORE and VIO pins)

(2)

–0.3

VCC + 0.3

Voltage applied to VIO pins

–0.3

VIO + 0.2

Diode current at any device pin

±2

Storage temperature, Tstg

(3)

–55

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3)

Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2

ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±1000

V(ESD) Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3

Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

Supply voltage during program execution and flash

VCC

programming (AVCC = DVCC)

(1) (2) (3)

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

VIO

Supply voltage applied to DVIO referenced to VSS

(2)

1.62

1.98

VSS

Supply voltage (AVSS = DVSS)

Operating free-air temperature

–40

°C

Operating junction temperature

–40

°C

CVCORE

Recommended capacitor at VCORE(4)

470

CDVCC/

Capacitor ratio of DVCC to VCORE

CVCORE

(1)

TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

During VCC and VIO power up, it is required that VIO ≥ VCC during the ramp up phase of VIO. During VCC and VIO power down, it is

required that VIO ≥ VCC during the ramp down phase of VIO (see Figure 5-1).

(3)

The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for

the exact values and further details.

(4)

TI recommends a capacitor tolerance of ±20% or better.

Specifications

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