WM8994 datasheet(154/359 Pages) WOLFSON

154 / 359 page

WM8994

Production Data

PD, April 2012, Rev 4.4

154

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10:9

AIF2DRC_SIG_D

ET_PK [1:0]

AIF2 DRC Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be

indicated when

AIF2DRC_SIG_DET_MODE=0.

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF2DRC_SIG_D

ET_MODE

AIF2 DRC Signal Detect Mode

0 = Peak threshold mode

1 = RMS threshold mode

AIF2DRC_SIG_D

AIF2 DRC Signal Detect Enable

0 = Disabled

1 = Enabled

Table 84 DRC Signal Activity Detect GPIO/Interrupt Control

CONTROL WRITE SEQUENCER STATUS DETECTION

The WM8994 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write

operations in response to a simple trigger event. When the Control Write Sequencer is executing a

sequence, normal access to the register map via the Control Interface is restricted. See “Control Write

Sequencer” for details of the Control Write Sequencer.

The WM8994 generates a signal indicating the status of the Control Write Sequencer, in order to

signal to the host processor whether the Control Interface functionality is restricted due to an ongoing

Control Sequence. The WSEQ_DONE flag indicates that the sequencer has completed the

commanded sequence.

The Write Sequencer status may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The Write Sequencer status is an input to the Interrupt control circuit. An interrupt event is triggered

on completion of a Control Sequence. The associated interrupt bit is latched once set; it can be polled

at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

DIGITAL CORE FIFO ERROR STATUS DETECTION

The WM8994 monitors the Digital Core for error conditions which may occur if a clock rate mismatch

is detected. Under these conditions, the digital audio may become corrupted.

The most likely cause of a Digital Core FIFO Error condition is an incorrect system clocking

configuration. See “Clocking and Sample Rates” for the WM8994 system clocking requirements.

The Digital Core FIFO Error function is provided in order that the system configuration can be verified

during product development.

The FIFO Error signal may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The FIFO Error signal is an input to the Interrupt control circuit. An interrupt event is triggered on the

rising edge of the FIFO Error signal. The associated interrupt bit is latched once set; it can be polled

at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

WM8994 Datasheet(PDF) 154 Page - Wolfson Microelectronics plc

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