WM8994 datasheet(152/359 Pages) WOLFSON

152 / 359 page

WM8994

Production Data

PD, April 2012, Rev 4.4

152

FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT

The WM8994 maintains a flag indicating the lock status of each of FLLs, which may be used to

control other events if required. See “Clocking and Sample Rates” for more details of the FLL.

The FLL Lock signals may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The FLL Lock signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the

rising and falling edges of the FLL Lock signals. The associated interrupt bits are latched once set;

they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of

the Interrupt event handling.

SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT

The WM8994 maintains a flag indicating the lock status of each of Sample Rate Converters, which

may be used to control other events if required. See “Sample Rate Conversion” for more details of the

Sample Rate Converters.

The SRC Lock signals may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The SRC Lock signals are inputs to the Interrupt control circuit, after the selectable de-bounce. An

interrupt event is triggered on the rising and falling edges of the SRC Lock signals. The associated

interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See “Interrupts” for more details of the Interrupt event handling.

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION

Signal activity detection is provided on each of the Dynamic Range Controllers (DRCs). These may

be configured to indicate when a signal is present on the respective signal path. The signal activity

status signals may be used to control other events if required. See “Digital Core Architecture” for

more details of the DRCs and the available digital signal paths.

When a DRC is enabled, as described in “Dynamic Range Control (DRC)”, then signal activity

detection can be enabled by setting the respective [DRC]_SIG_DET register bit. The applicable

threshold can be defined either as a Peak level (Crest Factor) or an RMS level, depending on the

[DRC]

_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by

[DRC]

_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If

RMS level is selected, then the threshold is set using [DRC]_SIG_DET_RMS. These register fields

are set independently for each of the three Dynamic Range Controllers, as described in Table 84.

The DRC Signal Detect signals may be output directly on any GPIO pin by setting the respective

GPIO registers as described in “GPIO Control”.

The DRC Signal Detect signals are inputs to the Interrupt control circuit. An interrupt event is

triggered on the rising edge of the DRC Signal Detect signals. The associated interrupt bits are

latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for

more details of the Interrupt event handling.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1088

(0440h)

AIF1 DRC1

(1)

15:11

AIF1DRC1_SIG_

DET_RMS [4:0]

00000

AIF1 DRC1 Signal Detect RMS

Threshold.

This is the RMS signal level for signal

detect to be indicated when

AIF1DRC1_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

WM8994 Datasheet(PDF) 152 Page - Wolfson Microelectronics plc

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