TMS320DM642 datasheet(142/178 Pages) TI

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Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 5-59. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

(1) (2)

(see Figure 5-56)

–500

–600

–720

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 – 12P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 24P

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2)

For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5-60. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 11b, CLKXP = 1

(1) (2) (see Figure 5-56)

–500

–600

–720

NO.

PARAMETER

UNIT

MASTER(3)

SLAVE

MIN

MAX

MIN

MAX

th(CKXH-FXL)

Hold time, FSX low after CLKX high(4)

H – 2

H + 3

td(FXL-CKXL)

Delay time, FSX low to CLKX low(5)

T – 2.5

T + 1.5

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–2

12P + 3

20P + 17

Disable time, DX high impedance following last data bit

tdis(CKXH-DXHZ)

–2

12P + 3

20P + 17

from CLKX high

td(FXL-DXV)

Delay time, FSX low to DX valid

L – 2

L + 4

8P + 2

16P + 17

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2)

For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3)

S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4)

FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5)

FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

Figure 5-56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

142

DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 142 Page - Texas Instruments

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