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TMS320DM642 Datasheet(PDF) 145 Page - Texas Instruments |
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TMS320DM642 Datasheet(HTML) 145 Page - Texas Instruments |
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145 / 178 page  www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Table 5-61. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (continued) HEX ADDRESS RANGE ACRONYM DESCRIPTION VP0 VP1 VP2 01C4 024C 01C4 424C 01C4 824C VD_VSYNE2x Video Display Field 2 Vertical Synchronization End Register 01C4 0250 01C4 4250 01C4 8250 VD_RELOADx Video Display Counter Reload Register 01C4 0254 01C4 4254 01C4 8254 VD_DISPEVTx Video Display Display Event Register 01C4 0258 01C4 4258 01C4 8258 VD_CLIPx Video Display Clipping Register 01C4 025C 01C4 425C 01C4 825C VD_DEFVALx Video Display Default Display Value Register 01C4 0260 01C4 4260 01C4 8260 VD_VINTx Video Display Vertical Interrupt Register 01C4 0264 01C4 4264 01C4 8264 VD_FBITx Video Display Field Bit Register 01C4 0268 01C4 4268 01C4 8268 VD_VBIT1x Video Display Field 1Vertical Blanking Bit Register 01C4 026C 01C4 426C 01C4 826C VD_VBIT2x Video Display Field 2Vertical Blanking Bit Register 7400 000 7800 0000 7C00 0000 Y_RSCA Y FIFO Source Register A 7400 0008 7800 0008 7C00 0008 CB_SRCA CB FIFO Source Register A 7400 0010 7800 0010 7C00 0010 CR_SRCA CR FIFO Source Register A 7400 0020 7800 0020 7C00 0020 Y_DSTA Y FIFO Destination Register A 7400 0028 7800 0028 7C00 0028 CB_DST CB FIFO Destination Register 7400 0030 7800 0030 7C00 0030 CR_DST CR FIFO Destination Register 7600 0000 7A00 0000 7E00 0000 Y_SRCB Y FIFO Source Register B 7600 0008 7A00 0008 7E00 0008 CB_SRCB CB FIFO Source Register b 7600 0010 7A00 0010 7E00 0010 CR_SRCB CR FIFO Source Register B 7600 0020 7A00 0020 7E00 0020 Y_DSTB Y FIFO Destination Register B DM642 Peripheral Information and Electrical Specifications 145 |
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