AD9864 datasheet(37/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 36 of 47

approximately 10 µs, while at the lowest setting the attenuation

changes from 0 dB to 12 dB in approximately 1.2 ms. In both

cases, assume that fCLK = 18 MHz. Figure 63 shows the AGC

attack time response for different AGCO settings.

AGCA = 0

TIME (ms)

AGCA = 4

AGCA = 8

AGCD = 8

AGCD = 0

AGCD = 8

AGCD = 0

AGCD = 8

AGCD = 0

Figure 62. AGC Response for Different AGCA and AGCD Settings with

fCLK = 18 MSPS, fCLKOUT = 20 kSPS, Decimate by 900, and AGCO = 0

TIME (ms)

0.1

0.2

0.5

0.4

0.3

1.0

0.9

0.8

0.7

0.6

112

128

AGCO = 7

AGCO = 4

AGCD = 0

Figure 63. AGC Response for Different AGCO Settings with fCLK = 18 MSPS,

fCLKOUT = 300 kSPS, Decimate by 60 and AGCA = AGCD = 0

Lastly, the AGCF bit reduces the DAC source resistance by at

least a factor of 10, which facilitates fast acquisition by lowering

the RC time constant that is formed with the external capacitors

connected from the GCP pin to ground (GCN pin). For an

overshoot-free step response in the AGC loop, choose the

capacitor connected from the GCP pin to the GCN ground

pin so that the RC time constant is less than one quarter of the

raw loop.

Specifically,

RC < 1/(8πBW)

(11)

where:

R is the resistance between the GCP pin and ground

(72.5 kΩ ±30% if AGCF = 0, < 8 kΩ if AGCF = 1).

BW is the raw loop bandwidth.

Note that with C chosen at this upper limit, the loop bandwidth

increases by approximately 30%.

Now consider the case described previously but with the DVGA

enabled to minimize the effects of 16-bit truncation. With the

DVGA enabled, a control loop based on the larger of the two

estimated signal levels (that is, the output of DEC1 and DVGA)

controls the DVGA gain. The DVGA multiplies the output of

the decimation filter by a factor of 1 to 4 (that is, 0 dB to 12 dB).

When signals are small, the DVGA gain is 4 and the 16-bit output

is extracted from the 24-bit data produced by the decimation

filter by dropping 2 MSB and taking the next 16 bits. As signals

become larger, the DVGA gain decreases to the point where the

DVGA gain is 1 and the 16-bit output data is simply the 16 MSB

of the internal 24-bit data. As signals become even larger,

attenuation is accomplished by the normal method of

increasing the full scale of the ADC.

The extra 12 dB of gain range provided by the DVGA reduces

the input-referred truncation noise by 12 dB and makes the

data more tolerant of LSB corruption within the DSP. The price

paid for this extension to the gain range is that the start of AGC

action is 12 dB lower and that the AGC loop becomes unstable

if its bandwidth is set too wide. The latter difficulty results from

the large delay of the decimation filters, DEC2 and DEC3, when

the user implements a large decimation factor. As a result, given

the option, the use of 24-bit data is preferable to using the

DVGA. Figure 64 indicates which AGCA values are reasonable

for various decimation factors (DEC FAC). The white cells

indicate that the (decimation factor/AGCA) combination works

well; the light gray cells indicate ringing and an increase in the

AGC settling time; and the dark gray cells indicate that the

combination results in instability or near instability in the AGC

loop. Setting AGCF = 1 improves the time-domain behavior at

the expense of increased spectral spreading.

AGCA

10 11 12 13 14 15

120

300

540

900

Figure 64. AGCA Limits when DVGA is Enabled

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