AD9864 datasheet(46/48 Pages) AD

46 / 48 page

Data Sheet

AD9864

Rev. A | Page 45 of 47

LAYOUT EXAMPLE, EVALUATION BOARD, AND

SOFTWARE

The evaluation platform and its accompanying software provide

a simple way to evaluate the AD9864. Figure 77 shows the

AD9864 evaluation board connected to the HSC-ADC-

EVALCZ data capture card in its simplest configuration with

only an external 5 V lab supply and RF signal generator

required for the AD6676 evaluation board. The evaluation

board is designed to be flexible, supporting different IFs as well

as LO and CLK generation schemes. An alternative right angle

18-pin header is available for monitoring digital input/output

signals or interfacing to other FPGA, DSP, or microcontroller

development platforms. The evaluation board also serves as a

layout example.

The power supply distribution block provides filtered,

adjustable voltages to the main core of the AD9864 as well as

the digital input/output supply. In the IF input signal path,

component pads are available to implement different IF

impedance matching networks. The LO and CLK signals can be

externally applied or internally derived from on-board VCOs

supporting the on-chip LO and CLK synthesizers. The reference

for the on-chip LO and CLK synthesizers can be applied via the

external fREF input or an via the on-board crystal oscillator.

Figure 77. Evaluation Board Platform

A simple software SPI control graphical user interface (GUI)

provides a ways to configure the AD9864. Analog Devices

VisualAnalog software is used for real-time data analysis. These

programs have a convenient GUI that allows easy access to the

various SPI port configuration registers and frequency/time

domain analysis of the output data.

SPI INITIALIZATION EXAMPLE

Table 24 shows an example SPI initialization sequence that is

used to configure the device when using both the on-chip LO

and CLK synthesizer. Note the following:



Step 4 through Step 10 can be avoided if an external clock

is supplied. Note that clock synthesizer and oscillator must

also be disabled in Step 3 (0x00 = 0x7F) and remain disabled

in Step 15 (0x70 or 0x30 depending on the LO synthesizer

being enabled).



Step 20 to Step 24 can be avoided if an external LO source

is supplied.



Wait states are included for both tuning procedure and

clock synthesizer (if used).

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