Data Sheet

AD9864

Rev. A | Page 15 of 47

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI is a bidirectional serial port. It is used to load the configuration information into the registers listed in Table 6, as well as to read

back their contents. Table 6 provides a list of the registers that can be programmed through the SPI port. Addresses and default values are

given in hexadecimal form.

Table 6. SPI Address Map

Address

(Hex)

Bit(s)

Width

Default

Value

Name

Description

Power Control Registers

0x00

[7:0]

8

0xFF

STBY

Standby control bits (REF, LO, CKO, CK, GC, LNAMX, unused, and ADC).

Default is power-up condition of standby.

0x01

[3:2]

2

0x00

CKOB

CK oscillator bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA, 3 = 0.65 mA).

[1:0]

2

0x00

ADCB

Do not use.

0x02

[7:0]

8

0x00

TEST

Factory test mode. Do not use.

AGC

0x03

7

1

0

ATTEN

Apply 16 dB attenuation in the front end.

[6:0]

7

0x00

AGCG [14:8]

AGC attenuation setting (7 MSBs of a 15-bit unsigned word).

0x04

[7:0]

8

0x00

AGCG [7:0]

AGC attenuation setting (8 LSBs of a 15-bit unsigned word).

0x05

[7:4]

4

0x00

AGCA

AGC attack bandwidth setting. Default yields 50 Hz loop bandwidth.

[3:0]

4

0x00

AGCD

AGC decay time setting. Default is decay time = attack time.

0x06

7

1

0

AGCV

Enable digital VGA to increase AGC range by 12 dB.

[6:4]

3

0x00

AGCO

AGC overload update setting. Default is slowest update.

3

1

0

AGCF

Fast AGC (minimizes resistance seen between GCP and GCN).

[2:0]

3

0x00

AGCR

AGC enable/reference level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB

below clip).

Decimation Factor

0x07

[7:5]

3

Unused

4

1

0

K

Decimation factor = 60 × (M + 1), if K = 0; 48 × (M + 1), if K = 1.

[3:0]

4

0x04

M

Default is decimate-by-300.

LO Synthesizer

0x08

[5:0]

6

0x00

LOR [13:8]

Reference frequency divider (6 MSBs of a 14-bit word).

0x09

[7:0]

8

0x38

LOR [7:0]

Reference frequency divisor (8 LSBs of a 14-bit word). Default (56) yields

0x0A

[7:5]

3

0x05

LOA

A counter (prescaler control counter).

[4:0]

5

0x00

LOB [12:8]

B counter MSB (5 MSB of a 13-bit word). Default LOA and LOB values

yield 300 kHz from 73.35 MHz to 2.25 MHz.

0x0B

[7:0]

8

0x1D

LOB [7:0]

B counter LSB (8 LSB of a 13-bit word).

0x0C

6

1

0

LOF

Enable fast acquire.

5

1

0

LOINV

Invert charge pump (0 = source current to increase VCO frequency).

[4:2]

3

0x00

LOI

[1:0]

2

0x03

LOTM

Manual control of LO charge pump (0 = off, 1 = up, 2 = down, and

3 = normal).

0x0D

[5:0]

6

0x00

LOFA [13:8]

LO fast acquire time unit (6 MSBs of a 14-bit word).

0x0E

[7:0]

8

0x04

LOFA [7:0]

LO fast acquire time unit (8 LSBs of a 14-bit word).

Clock Synthesizer

0x10

[5:0]

6

0x00

CKR [13:8]

Reference frequency divisor (6 MSBs of a 14-bit word).

0x11

[7:0]

8

0x38

CKR [7:0]

Reference frequency divisor (8 LSBs of a 14-bit word). Default yields

0x12

[4:0]

5

0x00

CKN [12:8]

Synthesized frequency divisor (5 MSBs of a 13-bit word).

0x13

[7:0]

8

0x3C

CKN [7:0]

Synthesized frequency divisor (8 LSBs of a 13-bit word). Default yields

300 kHz from 18 MHz; minimum = 3, maximum = 8191.