AD9864 datasheet(39/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 38 of 47

undergoes noise shaping just prior to 16-bit truncation, thus

reducing the in-band quantization noise by 5 dB (with 2×

oversampling). Therefore, 98.8 dBFS SNR performance is still

achievable with 16-bit data in a 10 kHz BW.

SNR = 98.8dBFS

BW = 50kHz

BW = 150kHz

SNR = 83dBFS

SNR = 94.1dBFS

BW = 10kHz

SNR = 89.9dBFS

VGA ATTENUATION (dB)

Figure 67. Nominal System Noise Figure and Peak SNR vs. AGCG Setting

(fIF = 73.35 MHz, fCLK = 18 MSPS, and 16-bit I/Q Data)

APPLICATIONS CONSIDERATIONS

Frequency Planning

The LO frequency (and/or ADC clock frequency) must be

chosen carefully to prevent known internally generated spurs

from mixing down along with the desired signal and thus

degrading the SNR performance. The major sources of spurs in

the AD9864 are the ADC clock and digital circuitry operating

at 1/3 of fCLK. Therefore, the clock frequency (fCLK) is the most

important variable in determining which LO (and therefore IF)

frequencies are viable.

Many applications have frequency plans that take advantage of

industry-standard IF frequencies due to the large selection of

low cost crystal or SAW filters. If the selected IF frequency and

ADC clock rate result in a problematic spurious component,

select an alternative ADC clock rate by slightly modifying the

decimation factor and CLK synthesizer settings (if used) so that

the output sample rate remains the same. Also, applications

requiring a certain degree of tuning range must take into

consideration the location and magnitude of these spurs when

determining the tuning range as well as optimum IF and ADC

clock frequency.

Figure 69 plots the measured in-band noise power as a function

of the LO frequency for fCLK = 18 MHz and an output signal

bandwidth of 150 kHz when no signal is present. Any LO

frequency resulting in large spurs must be avoided. As this

figure shows, large spurs result when the LO is fCLK/8 = 2.25 MHz

away from a harmonic of 18 MHz , that is, n fCLK ± fCLK/8. Also

problematic are LO frequencies whose odd order harmonics (that

is, m × fLO) mix with harmonics of fCLK to fCLK/8. This spur

mechanism is a result of the mixer being internally driven by a

squared-up version of the LO input consisting of the LO frequency

and its odd order harmonics. These spur frequencies can be

calculated from the relation

m × fLO = (n ± 1/8) × fCLK

(12)

where:

m = 1, 3, 5...

n = 1, 2, 3...

A second source of spurs is a large block of digital circuitry that

is clocked at fCLK/3. Problematic LO frequencies associated with

this spur source are given by

fLO = fCLK/3 + n × fCLK ± fCLK/8

(13)

where n = 1, 2, 3...

Figure 70 shows that omitting the LO frequencies given by

Equation 12 for m = 1, 3, and 5, and by Equation 13 accounts

for most of the spurs. Some of the remaining low level spurs can

be attributed to coupling from the SSI digital output. Therefore,

users are also advised to optimize the output bit rate (fCLKOUT via

the SSIORD register) and the digital output driver strength to

achieve the lowest spurious and noise figure performance for a

particular LO frequency and fCLK setting. This is especially the

case for particularly narrow-band channels where low level

spurs can degrade the sensitivity performance of the AD9864.

Despite the many spurs, sweet spots in the LO frequency are

generally wide enough to accommodate the maximum signal

bandwidth of the AD9864. As evidence of this property,

Figure 68 shows that the in-band noise is quite constant for LO

frequencies ranging from 70 MHz to 71 MHz.

70.5

70.0

–50

–70

–60

–90

–80

71.0

LO FREQUENCY (MHz)

Figure 68. Expanded View from 70 MHz to 71 MHz

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