AD9864 datasheet(25/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 24 of 47

SYNCHRONIZATION USING SYNCB

Many applications require the ability to synchronize one or

more AD9864 devices in a way that causes the output data to

be precisely aligned to an external asynchronous signal. For

example, receiver applications employing diversity often require

synchronization of the digital outputs of multiple AD9864

devices. Satellite communication applications using TDMA

methods may require synchronization between payload bursts

to compensate for reference frequency drift and Doppler effects.

SYNCB can be used for this purpose. It is an active-low signal

that clears the clock counters in both the decimation filter and

the SSI port. The counters in the clock synthesizers are not reset

because it is presumed that the CLK signals of multiple chips

would be connected. SYNCB also resets the modulator,

resulting in a large-scale impulse that must propagate through

the digital filter and SSI data formatting circuitry of the

AD9864 before recovering valid output data. As a result, data

samples unaffected by this SYNCB induced impulse can be

recovered 12 output data samples after SYNCB goes high

(independent of the decimation factor). Because SYNCB also

resets the modulator, apply SYNCB only after the tuning of the

band-pass Σ-Δ ADC has been completed during the

initialization phase. For applications that may be performing a

periodic SYNCB signal that is synchronous to FS, it is

recommended that SYNCB assertion be applied after the rising

edge of FS and three CLKOUT cycles before the arrival of the

next FS pulse to avoid a possible runt FS pulse that could

disrupt the host DSP/FPGA. Lastly, SYNCB must be tied high if

unused because it does not include an internal pull-up resistor.

Figure 37 shows the timing relationship between SYNCB and

the CLKOUT and FS signals of the SSI port. When the clock

synthesizer is enabled to generate the input ADC clock, SYNCB

is considered an asynchronous active-low signal that must remain

low for at least half an input clock period, that is, 1/(2 × fCLK).

CLKOUT remains high while FS remains low upon SYNCB

going low. CLKOUT becomes active within one to two output

clock periods upon SYNCB returning high. If an external ADC

clock input is supplied along with a synchronous SYNCB signal,

it is recommended that SYNCB go low and returns high on the

falling edges of the CLKIN signal to ensure consistent CLKOUT

delay relative to rising edge of SYNCB. FS reappears several

output cycles later, depending on the decimation factor of the

digital filter and the SSIORD setting. Note that for any

decimation factor and SSIORD setting, this delay is fixed and

repeatable. To verify proper synchronization, monitor the FS

signals of the multiple AD9864 devices.

SYNCB

CLKOUT

Figure 37. SYNCB Timing

INTERFACING TO DSPS

The AD9864 connects directly to an Analog Devices

programmable digital signal processor (DSP). Figure 38

illustrates an example with the Blackfin® series processors, such

as the ADSP-BF609. The Blackfin DSP series of 16-bit products

is optimized for low power telecommunications applications

with its dynamic power management feature, making it well

suited for portable radio products. The code compatible family

members share the fundamental core attributes of high

performance, low power consumption, and the ease-of-use

advantages of a microcontroller instruction set.

As shown in Figure 38, the synchronous serial interface (SSI)

of the AD9864 links the receive data stream to the serial port

(SPORT) of the DSP. For AD9864 setup and register

programming, the device connects directly to the SPI port of

the DSP. Dedicated select lines (SEL) allow the DSP to program

and read back registers of multiple devices using only one SPI

port. The DSP driver code pertaining to this interface is

available on the AD9864 product page.

AD9864

CLKOUT

SPORT0_ACLK

SPI1_CLK

SPI1_MOSI

DOUTB

SPI1_MISO

SPI1_SSEL7

SPORT0_AFS

DOUTA

SPORT0_AD0

SPI

SSI

ADSP-BF609

SPORT

SPI

SYNCB

PE0

DGND

GND

DGND

GND

Figure 38. Example of AD9864 and ADSP-BF609 Interface

POWER CONTROL

To allow power consumption to be minimized, the AD9864

possesses numerous SPI programmable power-down and bias

control bits. The AD9864 powers up with all of its functional

blocks placed into a standby state, that is, STBY register default

is 0xFF. Each major block can then be powered up by writing a

0 to the appropriate bit of the STBY register. This scheme

provides the greatest flexibility for configuring the IC to a

specific application as well as for tailoring the power-down and

wake-up characteristics of the IC. Table 16 summarizes the

function of each of the STBY bits. Note that when all the blocks

are in standby, the master reference circuit is also put into

standby, and therefore the current is reduced further by 0.4 mA.

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