AD9864 datasheet(41/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 40 of 47

EXTERNAL PASSIVE COMPONENT REQUIREMENTS

Figure 72 shows an example circuit using the AD9864 and

Table 23 shows the nominal dc bias voltages seen at the different

pins. The purpose is to show the various external passive

components required by the AD9864, along with nominal dc

voltages for troubleshooting purposes.

MXOP

MXON

GNDF

IF2N

IF2P

VDDF

GCP

GCN

VDDA

GNDA

VREFP

VREFN

GNDL

FREF

GNDS

SYNCB

GNDH

DOUTB

DOUTA

CLKOUT

VDDH

VDDD

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

AD9864

50Ω

180pF

100pF

100

2.2nF

100pF

10nF

100pF

100kΩ

10nF

Figure 72. Example Circuit Showing Recommended Component Values

Table 23. Nominal DC Bias Voltages

Pin Number

Mnemonic

Nominal DC Bias (V)

MXOP

VDDI − 0.2

MXON

VDDI − 0.2

IF2N

1.3 − 1.7

IF2P

1.3 − 1.7

VREFP

VDDA/2 + 0.250

VREFN

VDDA/2 − 0.250

RREF

1.2

CLKP

VDDC − 1.3

CLKN

VDDC − 1.3

FREF

VDDC/2

CXVM

1.6 − 2.0

LON

1.65 − 1.9

LOP

1.65 − 1.9

CXVL

VDDI − 0.05

CXIF

1.6 − 2.0

IFIN

0.9 − 1.1

The LO, CLK, and IFIN signals are coupled to their respective

inputs using 10 nF capacitors. The output of the mixer is

coupled to the input of the ADC using 100 pF. An external

100 kΩ resistor from the RREF pin to GND sets up the internal

bias currents of the AD9864. VREFP and VREFN provide a

differential reference voltage to the Σ-∆ ADC of the AD9864,

and must be decoupled by a 0.01 µF differential capacitor along

with two 100 pF capacitors to GND. The remaining capacitors

are used to decouple other sensitive internal nodes to GND.

Note that SYNCB is tied to VDDH because it is unused.

Although power supply decoupling capacitors are not shown, it

is recommended that a 0.1 µF surface-mount capacitor be

placed as close as possible to each power supply pin for

maximum effectiveness. Also not shown is the input impedance

matching network used to match the IF input of the AD9864 to

the external IF filter. Lastly, the loop filter components

associated with the LO and CLK synthesizers are not shown.

LC component values for fCLK = 18 MHz are given in Figure 72.

For other clock frequencies, the two inductors and the capacitor

of the LC tank must be scaled in inverse proportion to the

clock. For example, if fCLK = 26 MHz, the two inductors must be

6.9 µH and the capacitor must be approximately 120 pF. A

tolerance of 10% is sufficient for these components because

tuning of the LC tank is performed upon system startup.

APPLICATIONS

Superheterodyne Receiver Example

The AD9864 is well suited for analog and/or digital narrow-

band radio systems based on a superheterodyne receiver

architecture. The superheterodyne architecture is noted for

achieving exceptional dynamic range and selectivity by using

two or more downconversion stages to provide amplification of

the target signal while filtering the undesired signals. The

AD9864 greatly simplifies the design of these radio systems by

integrating the complete IF strip (excluding the LO VCO) while

providing an I/Q digital output (along with other system

parameters) for the demodulation of both analog and digital

modulated signals. The exceptional dynamic range of the

AD9864 often simplifies the IF filtering requirements and

eliminates the need for an external AGC.

AD9864 Datasheet(PDF) 41 Page - Analog Devices

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