AD9864 datasheet(47/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 46 of 47

DEVICE SPI INITIALIZATION

Table 24 shows an example SPI initialization script when both the CLK SYN/OSC and LO SYN are used.

Table 24. SPI Initialization Example, fCLKIN = 16.8 MHz, fADC = 18 MHz, fIF = 73.35 MHz, LO = 71.10 MHz, fDATA_IQ = 60 kSPS with

Decimate by 300

Step

Address (Hex)

Write Value

Description

0x3F

0x99

Software reset.

0x19

0x87

Enable 4-wire SPI readback while keeping default 16-bit I/Q word width and maximum CMOS

output drive strength.

0x00

0x45

Take REF, GC, and CLK SYN/LO out of standby.

Configure Clock Synthesizer

0x01

0x0C

Set the CK oscillator bias to 0.65 mA for maximum swing.

0x10

0x00

Set the CLK synthesizer MSB and LSB reference frequency divider. (Note that default setting is

shown resulting in divide by 56.)

0x11

0x38

0x12

0x00

Set the CLK synthesizer MSB and LSB reference frequency divider. (Note that default setting is

shown resulting in divide by 300.)

0x13

0x3C

0x14

0x03

Set the CLK synthesizer charge pump to 0.625 mA. (Note that setting depends on PLL loop

configuration.)

Not applicable

Wait until the CLK SYN output frequency settles to within 0.01% of final frequency.

Begin LC and RC Resonator Calibration

0x3E

0x47

Disable the internal ADC unstable signal. Enable RC Q enhancement, and bypass the RC and SC

resonators.

0x38

0x01

Enable manual control of feedback DAC.

0x39

0x0F

Set DAC to midscale.

0x1C

0x03

Set LC and RC tuning bits.

0x00

0x44

Bring ADC out of standby to initiate LC and RC calibration.

0x1C

Readback value

Wait 6 ms and read back Register 0x1C. If Register 0x1C clears, proceed to Step 17. If Register 0x1C

does not clear, reset Register 0x1C and return to Step 14. Make five attempts before exiting loop.

0x38

0x00

Disable manual control of feedback DAC.

0x3E

0x00

Re-enable ADC unstable signal, disable RC_Q enhancement, and disable bypass of RC and SC

resonators.

End of LC and RC Resonator Calibration

0x00

Bring LNA/Mixer and LO synthesizer out of standby.

Configure LO Synthesizer

0x08

0x00

Set the LO synthesizer MSB and LSB reference frequency divider. (Note that the default setting

is shown resulting in divide by 56.)

0x09

0x38

0x0A

0xA0

Set the LO synthesizer A and B counters. (Note that the default setting is shown resulting in

divide by 237.)

0x0B

0x1D

0x0C

0x03

Set the LO synthesizer charge pump to 0.625 mA. (Note that setting depends on PLL loop

configuration.)

Configure Remaining SPI Registers

0x03 to 0x07

Set AGC registers.

0x07

0x04

Set decimation factor to 300.

0x1A

0x01

Set SSIORD register, which determines the CLKOUT frequency.

0x18

0x40

Take FS and CLKOUT out of tristate and configure SSI frame format.

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