SLG46721 datasheet(44/101 Pages) DIALOG

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000-0046721-114

Page 43 of 100

SLG46721

10.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings

Table 41. DFF4 Register Settings

Signal Function

Address

LUT2_0 or DFF4

Select

595

0: LUT2_0

1: DFF4

DFF4 or Latch

Select

571

0: DFF function

1: Latch function

DFF4 Output Select

572

0: Q output

1: nQ output

DFF4 Initial Polarity

Select

573

0: Low

1: High

Table 42. DFF5 Register Settings

Signal Function

Address

LUT2_1 or DFF5

Select

596

0: LUT2_1

1: DFF5

Select or Latch

select

575

0: DFF function

1: Latch function

DFF5 Output Select

576

0: Q output

1: nQ output

DFF5 Initial Polarity

Select

577

0: Low

1: High

Table 43. DFF6 Register Settings

Signal Function

Address

LUT2_2 or DFF6

Select

597

0: LUT2_2

1: DFF6

DFF6 or Latch

Select

579

0: DFF function

1: Latch function

DFF6 Output Select

580

0: Q output

1: nQ output

DFF6 Initial Polarity

Select

581

0: Low

1: High

Table 44. DFF7 Register Settings

Signal Function

Address

LUT2_3 or DFF7

Select

598

0: LUT2_3

1: DFF7

DFF7 or Latch

Select

583

0: DFF function

1: Latch function

DFF7 Output Select

584

0: Q output

1: nQ output

DFF7 Initial Polarity

Select

585

0: Low

1: High

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