SLG46721 datasheet(95/101 Pages) DIALOG

95 / 101 page

000-0046721-114

Page 94 of 100

SLG46721

reg<968:967>

Select the edge mode of programmable delay & edge

detector

00: rising edge detector

01: falling edge detector

10: both edge detector

11: both edge delay

reg<969>

Select edge detector output mode

0: edge detector output

1: delayed edge detector output

reg<977:970>

8-bit pattern id

reg<978>

GPIO quick charge enable

0: Disable

1: Enable

reg<979>

NVM data read disable

0: Disable (program data can be read)

1: Enable (Program data cannot be read)

reg<980>

NVM power down

0: None (or programming enable)

1: Power Down (or programming disable)

reg<981>

Force bandgap on

0: Auto-mode

1: Enable

reg<982>

VREF1 Output Active Buffer Control

0: Disabled (bypass Active Buffer)

1: Enabled

reg<983>

VREF2 Output Active Buffer Control

0: Disabled (bypass Active Buffer)

1: Enabled

reg<991:984>

Reserved

reg<994:992>

VREF1 Output Source Select

000: ACMP0 reference voltage

001: ACMP1 reference voltage

100: VDD/2

101: VDD/3

110: VDD/4

111: Hi-Z

reg<997:995>

VREF2 Output Source Select

000: ACMP2 reference voltage

001: ACMP3 reference voltage

100: VDD/2

101: VDD/3

110: VDD/4

111: Hi-Z

reg<998>

Power Divider Power

0: Power down

1: Power On

reg<999>

POR Auto Power detect

0: Enable

1: Disable

reg<1000>

Charge pump for analog macrocell enable (when VDD

<=2.7V turn on)

0: Disable (automatic on/off control)

1: Enable (always on)

reg<1002:1001> Reserved

reg<1007:1003> Reserved

reg<1013:1008> Reserved

Reg<1015:1014> Reserved

reg<1023:1016> Reserved

Address

Signal Function

SLG46721 Datasheet(PDF) 95 Page - Dialog Semiconductor

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