SLG46721 datasheet(67/101 Pages) DIALOG

Part #	SLG46721

Description	Logic & Mixed Signal Circuits

PDF	101 Pages

Scroll/Zoom	100%

Manufacturer	DIALOG [Dialog Semiconductor]

Direct Link	http://www.dialog-semiconductor.com/

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67 / 101 page

000-0046721-114

Page 66 of 100

SLG46721

13.1 CNT/DLY Timing Diagrams

Figure 30. Delay Mode Timing

Figure 31. Counter Mode Timing

delay_in

RC osc: force power on

(always running)

Delay output

Asynchronous delay variable

delay = period x (counter data + 2) + variable

variable = 0..1

delay = period x (counter data + 2) + variable

variable = 0..1

Delay mode (edge select: both, counter data:3)

delay_in

RC osc: auto power on

(powers up from delay in)

Delay output

offset

delay = offset + period x (counter data + 2)

variable = 0..1

offset = approx. 4-22

s at room temp. for 2 MHz osc

delay = offset + period x (counter data + 2)

variable = 0..1

offset = approx. 4-22

s at room temp. for 2 MHz osc

delay_in

CLK

Counter output

Count start in 2 clk after reset

4 clk period pulse

Count mode (count data:3), Counter reset (rising edge detect reset by delay_in input)

SLG46721 Datasheet(PDF) 67 Page - Dialog Semiconductor