SLG46721 datasheet(83/101 Pages) DIALOG

83 / 101 page

000-0046721-114

Page 82 of 100

SLG46721

reg<485:480>

Matrix Out: Pin14 Output Enable

reg<491:486>

Matrix Out: Pin15 Digital Output Source

reg<497:492>

Matrix Out: Pin16 Digital Output Source

reg<503:498>

Matrix Out: Pin16 Output Enable

reg<509:504>

Matrix Out: Pin17 Digital Output Source

reg<515:510>

Matrix Out: Pin18 Digital Output Source

reg<521:516>

Matrix Out: Pin18 Output Enable

reg<527:522>

Matrix Out: Pin19 Digital Output Source

reg<533:528>

Matrix Out: Pin19 Output Enable

reg<539:534>

Matrix Out: Pin20 Digital Output Source

reg<545:540>

Matrix Out: Input of INV_0

reg<551:546>

Matrix Out: Input of INV_1

reg<556:552>

ACMP3 IN voltage select

00000: 50 mV

00001: 100 mV

00010: 150 mV

00011: 200 mV

00100: 250 mV

00101: 300 mV

00110: 350 mV

00111: 400 mV

01000: 450 mV

01001: 500 mV

01010: 550 mV

01011: 600 mV

01100: 650 mV

01101: 700 mV

01110: 750 mV

01111: 800 mV

10000: 850 mV

10001: 900 mV

10010: 950 mV

10011: 1 V

10100: 1.05V

10101: 1.1 V

10110: 1.15V

10111: 1.2 V

11000: VDD/3

11001: VDD/4

11010: EXT_VREF (PIN12)

11011: EXT_VREF (PIN14)

reg<558:557>

ACMP3 hysteresis Enable

00: Disabled (0 mV)

01: Enabled (25 mV)

10: Enabled (50 mV)

11: Enabled (200 mV)

reg<560:559>

ACMP3 positive Input divider

00: 1.0X

01: 0.5X

10: 0.33X

11: 0.25X

reg<561>

ACMP3 low bandwidth (typ: Max.1Mhz) enable.

0: Off

1: On

reg<562>

ACMP3 positive input source select PIN6

0: Disabled

1: Enabled

reg<563>

ACMP3 positive input source select PIN13

0: Disabled

1: Enabled

reg<564>

VDD bypass enable

0: Regulator auto on

1: Regulator off (VDD bypass)

reg<566:565>

OSC clock pre-divider

00: Div1

01: Div2

10: Div4

11: Div8

reg<568:567>

Reserved

reg<569>

Analog buffer at ACMP0 enable

0: Disable analog buffer

1: Enable analog buffer

Address

Signal Function

SLG46721 Datasheet(PDF) 83 Page - Dialog Semiconductor

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