| Electronic Components Datasheet Search |
|
SLG46721 Datasheet(PDF) 74 Page - Dialog Semiconductor |
|
|
|||||||||||||||||||||||||||||
SLG46721 Datasheet(HTML) 74 Page - Dialog Semiconductor |
|
74 / 101 page ![]() 000-0046721-114 Page 73 of 100 SLG46721 15.3 Programmable Delay Register Settings Table 65. Programmable Delay Register Settings Signal Function Register Bit Address Register Definition Delay value select for programmable delay & edge detector (VDD = 3.3V, typical condition) reg<966:965> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns Select the edge mode of programmable delay & edge detector reg<968:967> 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay Select edge detector output mode reg<969> 0: Non-Delayed Output 1: Delayed Output |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |