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SLG46721 Datasheet(PDF) 94 Page - Dialog Semiconductor |
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SLG46721 Datasheet(HTML) 94 Page - Dialog Semiconductor |
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94 / 101 page ![]() 000-0046721-114 Page 93 of 100 SLG46721 reg<936:935> PIN18 mode control (sig_pin18_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<938:937> PIN18 pull up/down resistor value selection 00: Floating 01: 10K 10: 100K 11: 1M reg<939> PIN18 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<941:940> PIN19 mode control (sig_pin19_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output reg<943:942> PIN19 mode control (sig_pin19_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<945:944> PIN19 pull up/down resistor value selection 00: Floating 01: 10K 10: 100K 11: 1M reg<946> PIN19 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<949:947> PIN20 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<951:950> PIN20 pull up/down resistor value selection 00: Floating 01: 10K 10: 100K 11: 1M reg<952> PIN20 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<953> PIN20 driver strength selection 0: 1X 1: 2X reg<961:954> LUT3_9 data reg<962> Filter_1 output polarity select 0: Filter_1 output 1: Filter_1 output inverted reg<963> LUT3_8 or pipe delay output select 0: LUT3_8 1: 1pipe delay output reg<964> Pipe delay OUT1 polarity select bit 0: non-inverted 1: inverted reg<966:965> Delay value select for programmable delay & edge de- tector (VDD = 3.3V, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns Register Bit Address Signal Function Register Bit Definition |
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