SLG46721 datasheet(46/101 Pages) DIALOG

46 / 101 page

000-0046721-114

Page 45 of 100

SLG46721

10.2.1 3-Bit LUT or D Flip Flop Macrocells Used as 3-Bit LUTs

Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT2 is defined by reg<622:615>

3-Bit LUT3 is defined by reg<630:623>

10.2.2 3-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings

Table 47. DFF2 Register Settings

Signal Function

Address

LUT3_2 or DFF2

Select

reg<671>

0: LUT3_2

1: DFF2

DFF2 or Latch

Select

reg<615>

0: DFF function

1: Latch function

DFF2 Output Select

reg<616>

0: Q output

1: nQ output

DFF2 rstb/setb

Select

reg<617>

1: setb from matrix out

0: resetb from matrix out

DFF2 Initial Polarity

Select

reg<618>

0: Low

1: High

Table 48. DFF3 Register Settings

Signal Function

Address

LUT3_3 or DFF3

Select

reg<672>

0: LUT3_3

1: DFF3

DFF3 or Latch

Select

reg<623>

0: DFF function

1: Latch function

DFF3 Output Select

reg<624>

0: Q output

1: nQ output

DFF3 rstb/setb

Select

reg<625>

1: setb from matrix out

0: resetb from matrix out

DFF3 Initial Polarity

Select

reg<626>

0: Low

1: High

Table 45. 3-bit LUT2 Truth Table.

IN2

IN1

IN0

OUT

reg <615>

reg <616>

reg <617>

reg <618>

reg <619>

reg <620>

reg <621>

reg <622>

Table 46. 3-bit LUT3 Truth Table.

IN2

IN1

IN0

OUT

reg <623>

reg <624>

reg <625>

reg <626>

reg <627>

reg <628>

reg <629>

reg <630>

SLG46721 Datasheet(PDF) 46 Page - Dialog Semiconductor

SLG46721 Datasheet(HTML) 46 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL