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SLG46721 Datasheet(PDF) 14 Page - Dialog Semiconductor |
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SLG46721 Datasheet(HTML) 14 Page - Dialog Semiconductor |
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14 / 101 page ![]() 000-0046721-114 Page 13 of 100 SLG46721 5.9 Typical Pulse Width Performance time2 Delay, 3 cell mode: both edge delay, delayed edge detect output 1600 680 480 ns time2 Delay, 4 cell mode: both edge delay, delayed edge detect output 1900 815 600 ns Table 5. Typical Pulse Width Performance. Parameter VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit Filtered Pulse Width < 150 < 55 < 35 ns Table 4. Expected Delays and Widths for Programmable Delay (typical). Symbol Parameter Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit |
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