SLG46721 datasheet(82/101 Pages) DIALOG

82 / 101 page

000-0046721-114

Page 81 of 100

SLG46721

reg<233:228>

Matrix Out: In0 of LUT3_1

reg<239:234>

Matrix Out: In1 of LUT3_1

reg<245:240>

Matrix Out: In2 of LUT3_1

reg<251:246>

Matrix Out: In0 of LUT3_2 or Clock Input of DFF2

reg<257:252>

Matrix Out: In1 of LUT3_2 or Data Input of DFF2

reg<263:258>

Matrix Out: In2 of LUT3_2 or Resetb Input of DFF2

reg<269:264>

Matrix Out: In0 of LUT3_3 or Clock Input of DFF3

reg<275:270>

Matrix Out: In1 of LUT3_3 or Data Input of DFF3

reg<281:276>

Matrix Out: In2 of LUT3_3 or Resetb (Setb) of DFF3

reg<287:282>

Matrix Out: In0 of LUT3_4

reg<293:288>

Matrix Out: In1 of LUT3_4

reg<299:294>

Matrix Out: In2 of LUT3_4

reg<305:300>

Matrix Out: In0 of LUT3_5

reg<311:306>

Matrix Out: In1 of LUT3_5

reg<317:312>

Matrix Out: In2 of LUT3_5

reg<323:318>

Matrix Out: In0 of LUT3_6

reg<329:324>

Matrix Out: In1 of LUT3_6

reg<335:330>

Matrix Out: In2 of LUT3_6

reg<341:336>

Matrix Out: In0 of LUT3_7

reg<347:342>

Matrix Out: In1 of LUT3_7

reg<353:348>

Matrix Out: In2 of LUT3_7

reg<359:354>

Matrix Out: In0 of LUT3_8 or Input of Pipe delay

reg<365:360>

Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay

reg<371:366>

Matrix Out: In2 of LUT3_8 or Clock of Pipe delay

reg<377:372>

Matrix Out: In0 of LUT2_0 or Clock Input of DFF4

reg<383:378>

Matrix Out: In1 of LUT2_0 or Data Input of DFF4

reg<389:384>

Matrix Out: In0 of LUT2_1 or Clock Input of DFF5

reg<395:390>

Matrix Out: In1 of LUT2_1 or Data Input of DFF5

reg<401:396>

Matrix Out: In0 of LUT2_2 or Clock Input of DFF6

reg<407:402>

Matrix Out: In1 of LUT2_2 or Data Input of DFF6

reg<413:408>

Matrix Out: In0 of LUT2_3 or Clock Input of DFF7

reg<419:414>

Matrix Out: In1 of LUT2_3 or Data Input of DFF7

reg<425:420>

Matrix Out: In0 of LUT2_4

reg<431:426>

Matrix Out: In1 of LUT2_4

reg<437:432>

Matrix Out: In0 of LUT2_5

reg<443:438>

Matrix Out: In1 of LUT2_5

reg<449:444>

Matrix Out: Input for programmable delay & edge detec-

tor

reg<455:450>

Matrix Out: Power down for osc

reg<461:456>

Matrix Out: Pin12 Digital Output Source (Super Drive)

reg<467:462>

Matrix Out: Pin13 Digital Output Source

reg<473:468>

Matrix Out: Pin13 Output Enable

reg<479:474>

Matrix Out: Pin14 Digital Output Source

Address

Signal Function

SLG46721 Datasheet(PDF) 82 Page - Dialog Semiconductor

SLG46721 Datasheet(HTML) 82 Page - Dialog Semiconductor

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