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SLG46721 Datasheet(PDF) 52 Page - Dialog Semiconductor

Part # SLG46721
Description  Logic & Mixed Signal Circuits
PDF  101 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46721 Datasheet(HTML) 52 Page - Dialog Semiconductor

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SLG46721
10.4.2 4-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 8-Bit Counter / Delay Register Settings
Table 54. CNT/DLY2 Register Settings
Signal Function
Register Bit
Address
Register Definition
LUT4_0 or
Counter2 Select
reg<705>
0: LUT4_0
1: Counter2
Counter/delay2
Mode Selection
reg<673>
0: Delay Mode
1: Counter Mode
Counter/delay2
Clock Source Select
reg<676:674>
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock / 8
111: Counter1 Overflow
Counter/delay2
Control Data
reg<684:677>
1 – 256 (delay time = (counter control data +2) /freq)
Delay2 Mode Select
or asynchronous
counter reset
reg<686:685>
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges / high level reset
Table 55. CNT/DLY3 Register Settings
Signal Function
Register Bit
Address
Register Definition
LUT4_1 or
Counter3 Select
reg<706>
0: LUT4_1
1: Counter3
Counter/delay3
Mode Selection
reg<689>
0: Delay Mode
1: Counter Mode
Counter/delay3
Clock Source Select
reg<692:690>
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock / 8
111: Counter2 Overflow
Counter/delay3
Control Data
reg<700:693>
1 – 256 (delay time = (counter control data +2) /freq)
Delay3 Mode Select
or asynchronous
counter reset
reg<702:701>
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges / high level reset



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