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SLG46721 Datasheet(PDF) 57 Page - Dialog Semiconductor |
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SLG46721 Datasheet(HTML) 57 Page - Dialog Semiconductor |
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57 / 101 page ![]() 000-0046721-114 Page 56 of 100 SLG46721 11.3 ACMP1 Block Diagram Figure 21. ACMP1 Block Diagram 11011 11010 11001- 00000 Internal Vref PIN12: ACMP1(-) PIN12: ACMP1(-) 110 100 0X1 PIN10: ACMP1(+) From ACMP0’s MUX output External VDD 2.7 V ~ 5.5 V Selectable Gain reg <814:813> Vref + - From Connection Matrix Output <13> pdb LBW Selection ibias reg <816> Hysteresis Selection reg <812:811> L/S ON after 100 s Delay To Connection Matrix Input <11> reg <810:806> *PIN10_aio_en; reg <570>; reg <817> *PIN10_aio_en: if reg <883:882>=’11’ then 1, otherwise: 0 |
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