SLG46721 datasheet(85/101 Pages) DIALOG

85 / 101 page

000-0046721-114

Page 84 of 100

SLG46721

reg<622:615>

LUT3_2 Data (if reg.<671>=0) or DFF2 / Latch Select)

reg<615> DFF2 or Latch select

0: DFF function

1: Latch function

reg<616> DFF2 output select

0: Q output

1: nQ output

reg<617> DFF2 rstb/setb select

0: resetb from matrix output

1: setb from matrix output

reg<618> DFF2 initial polarity select

0: Low

1: High

reg<630:623>

LUT3_3 Data (if reg.<672>=0) or DFF3 / Latch Select

reg<623> DFF3 or Latch select

0: DFF function

1: Latch function

reg<624> DFF3 output select

0: Q output

1: nQ output

reg<625> DFF3 rstb/setb select

0: resetb from matrix output

1: setb from matrix output

reg<626> DFF3 initial polarity select

0: Low

1: High

reg<638:631>

LUT3_4 data

reg<646:639>

LUT3_5 data

reg<654:647>

LUT3_6 data

reg<662:655>

LUT3_7 data

reg<670:663>

LUT3_8 data or pipe number select

reg<666:663>: OUT0 select

reg<670:667>: OUT1 select

reg<671>

LUT3_2 or DFF2 select

0: LUT3_2

1: DFF2

reg<672>

LUT3_3 or DFF3 select

0: LUT3_3

1: DFF3

reg<688:673>

LUT4_0 data or Counter / Delay 2 mode selection

reg<673> Counter/delay2 mode selection

0: Delay Mode

1: Counter Mode

reg<676:674> Counter/delay2 Clock Source select

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock/8

111: Counter1 Overflow

reg<684:677> Counter/delay2 Control Data

1 – 256 (delay time = (counter control data +2) /freq)

reg<686:685> Delay2 Mode Select or asynchronous

counter reset

00: on both falling and rising edges (for delay &

counter reset)

01: on falling edge only (for delay & counter reset)

10: on rising edge only (for delay & counter reset)

11: no delay on either falling or rising edges / high

level reset

Address

Signal Function

SLG46721 Datasheet(PDF) 85 Page - Dialog Semiconductor

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