PCI7510 datasheet(151/234 Pages) TI

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7–10

7.14 Interrupt Line Register

The interrupt line register communicates interrupt line routing information. See Table 7–11 for a complete description

of the register contents.

Bit

Name

Interrupt line

Type

Default

Interrupt line

Offset:

3Ch

Type:

Read/Write

Default:

00h

Table 7–11. Interrupt Line Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

7–0

INTR_LINE

Interrupt line. This field is programmed by the system and indicates to software which interrupt line the

PCI7510 PCI_INTA is connected to.

7.15 Interrupt Pin Register

The value read from this register is function dependent and depends on the values of bits 28, the tie-all bit (TIEALL),

and 29, the interrupt tie bit (INTRTIE), in the system control register (PCI offset 80h, see Section 4.30). The INTRTIE

bit is compatible with previous TI CardBus controllers, and when set to 1, ties INTB to INTA internally. The TIEALL

bit ties INTA, INTB, and INTC together internally. The internal interrupt connections set by INTRTIE and TIEALL are

communicated to host software through this standard register interface. This read-only register is described for all

PCI7510 functions in Table 7–12.

Bit

Name

Interrupt pin

Type

Default

Interrupt pin

Offset:

3Dh

Type:

Read-only

Default:

02h

Table 7–12. PCI Interrupt Pin Register—Read-Only INTPIN Per Function

INTRTIE BIT

(BIT 29, OFFSET 80h)

TIEALL BIT

(BIT 28, OFFSET 80h)

INTPIN

FUNCTION 0

(CARDBUS)

INTPIN

FUNCTION 1

(DEDICATED SOCKET)

INTPIN

FUNCTION 2

(1394 OHCI)

01h (INTA)

02h (INTB)

03h (INTC)

01h (INTA)

03h (INTC)

01h (INTA)

NOTE: When configuring the PCI7510 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior

to setting the INTRTIE bit.

PCI7510 Datasheet(PDF) 151 Page - Texas Instruments

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