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PCI7510 Datasheet(PDF) 156 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 156 Page - Texas Instruments |
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156 / 234 page  7–15 7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7–19 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI PHY control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI PHY control Type R R R R R R R R RW R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Register: PCI PHY control Offset: ECh Type: Read/Write, Read-only Default: 0000 0008h Table 7–19. PCI PHY Control Register BIT FIELD NAME TYPE DESCRIPTION 31–8 RSVD R Reserved. Bits 31–8 return 0s when read. 7 ‡ CNAOUT RW When bit 7 is set to 1, the PHY CNA output is routed to terminal 96. When implementing a serial EEPROM, this bit can be set by programming bit 7 of offset 16h in the EEPROM to 1. See Table 3–11, EEPROM Loading Map. 6–5 4 ‡ RSVD R Reserved. Bits 6–4 return 0s when read. These bits are affected when implementing a serial EEPROM; thus, bits 6–4 at EEPROM byte offset 16h must be programmed to 0. See Table 3–11, EEPROM Loading Map. 3 ‡ RSVD R Reserved. Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a-2000. If a serial EEPROM is implemented, then bit 3 at EEPROM byte offset 16h must be set to 1. See Table 3–11, EEPROM Loading Map. 2–0 RSVD R Reserved. Bits 2–0 return 0s when read. These bits are affected when implementing a serial EEPROM; thus, bits 2–0 at EEPROM byte offset 16h must be programmed to 0. See Table 3–11, EEPROM Loading Map. ‡ One or more bits in this register are cleared only by the assertion of GRST. 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7–20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI miscellaneous configuration Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI miscellaneous configuration Type RW R RW R RW RW RW RW R R R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: PCI miscellaneous configuration Offset: F0h Type: Read/Write, Read-only Default: 0000 0000h |
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