PCI7510 datasheet(164/234 Pages) TI

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8–5

8.2

GUID ROM Register

The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI

version register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8–3 for a complete description of the

Bit

Name

GUID ROM

Type

RSU

Default

Bit

Name

GUID ROM

Type

Default

GUID ROM

Offset:

04h

Type:

Read/Set/Update, Read/Update, Read-only

Default:

00XX 0000h

Table 8–3. GUID ROM Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

addrReset

RSU

Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the PCI7510 device completes

the reset, it clears this bit. The PCI7510 device does not automatically fill bits 23–16 (rdData field) with

the 0th byte.

30–26

RSVD

Reserved. Bits 30–26 return 0s when read.

rdStart

RSU

A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared

when the PCI7510 device completes the read of the currently addressed GUID ROM byte.

RSVD

Reserved. Bit 24 returns 0 when read.

23–16

rdData

This field contains the data read from the GUID ROM.

15–8

RSVD

Reserved. Bits 15–8 return 0s when read.

7–0

miniROM

The miniROM field defaults to 0 indicating that no mini-ROM is implemented. If bit 5 of EEPROM offset

6h is set to 1, then this field returns 20h indicating that valid mini-ROM data begins at offset 20h of the

GUID ROM.

PCI7510 Datasheet(PDF) 164 Page - Texas Instruments

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