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PCI7510 Datasheet(PDF) 220 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 220 Page - Texas Instruments |
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220 / 234 page ![]() 11–5 11.8 Header Type Register This read-only register indicates that this function has a standard PCI header type. Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 0 0 Register: Header type Offset: 0Eh Type: Read-only Default: 80h 11.9 BIST Register Because the PCI7510 device does not support a built-in self test (BIST), this read-only register returns the value of 00h when read. Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: BIST Offset: 0Fh Type: Read-only Default: 00h 11.10 Base Address Register This register specifies the base address of a 4-byte I/O space used for loading the PCI7510 firmware. See Table 11–5 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Base address Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Base address Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Base address Offset: 10h Type: Read-only, Read/Write Default: 0000 0001h Table 11–5. Base Address Register Description BIT SIGNAL TYPE FUNCTION 31–2 BAR RW Base address. This field specifies the upper 30 bits of the 32-bit starting base address. 1 RSVD R Reserved. Bit 1 returns 0 when read. 0 IO_INDICATOR R I/O space indicator. This bit is hardwired to 1 to indicate that the base address maps into I/O space. |
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