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PCI7510 Datasheet(PDF) 217 Page - Texas Instruments |
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PCI7510 Datasheet(HTML) 217 Page - Texas Instruments |
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217 / 234 page  11–2 11.2 Device ID Register This 16-bit read-only register contains the value 8204h assigned by TI to the PCI7510 firmware loading function. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 Register: Device ID Offset: 02h Type: Read-only Default: 8204h 11.3 Command Register This register provides control over the PCI7510 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 11–2 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R RW R RW R RW R RW R RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Command Offset: 04h Type: Read-only, Read/Write Default: 0000h Table 11–2. Command Register Description BIT SIGNAL TYPE FUNCTION 15–11 RSVD R Reserved. Bits 15–11 return 0s when read. 10 INT_DISABLE RW INTx disable. When set, this bit disables the function from asserting interrupts on the INTx signals. Since the firmware loader function does not signal interrupts, this bit has no effect on the function. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled This bit is disabled (read-only 0) if bit 0 (PCI2_3_EN) in the miscellaneous control register (see Section 11.24) is 0. 9 FBB_EN R Fast back-to-back enable. The PCI7510 device does not generate fast back-to-back transactions; thus, this bit returns 0 when read. 8 SERR_EN RW SERR enable. When set, the PCI7510 SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. 7 RSVD R Reserved. Bit 7 returns 0 when read. 6 PERR_EN RW Parity error enable. When set, the PCI7510 device is enabled to drive the PERR response to parity errors through the PERR signal. 5 VGA_EN R VGA palette snoop enable. The PCI7510 device does not feature VGA palette snooping; thus, this bit returns 0 when read. 4 MWI_EN RW Memory write-and-invalidate (MWI) enable. This bit is hardwired to 0 since the firmware loader is a slave-only function. 3 SPECIAL R Special cycle enable. The PCI7510 device does not respond to special cycle transactions. This bit returns 0 when read. 2 MASTER_ENB RW Bus master enable. This bit is hardwired to 0 since the firmware loader is a slave-only function. 1 MEMORY_ENB RW Memory response enable. This bit is hardwired to 0 since the firmware loader does not respond to memory cycles. 0 IO_EN RW I/O space enable. Setting this bit to 1 enables the PCI7510 device to respond to I/O space accesses. |
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