PCI7510 datasheet(218/234 Pages) TI

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11–3

11.4 Status Register

This register provides device information to the host system. Bits in this register may be read normally. A bit in the

status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions

adhere to the definitions in the PCI Local Bus Specification. See Table 11–3 for a complete description of the register

contents.

Bit

Name

Status

Type

RCU

Default

Status

Offset:

06h

Type:

Read-only, Read/Clear/Update

Default:

0210h

Table 11–3. Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

PAR_ERR

RCU

Detected parity error. This bit is set when a parity error is detected, either an address- or data-parity

error.

SYS_ERR

RCU

Signaled system error. This bit is set when SERR is enabled and the PCI7510 device has signaled a

system error to the host.

MABORT

RCU

Received master abort. This bit is set when a cycle initiated by the PCI7510 device on the PCI bus

has been terminated by a master abort.

TABORT_REC

RCU

Received target abort. This bit is set when a cycle initiated by the PCI7510 device on the PCI bus

has been terminated by a target abort.

TABORT_SIG

RCU

Signaled target abort. This bit is set by the PCI7510 device when it terminates a transaction on the

PCI bus with a target abort.

10–9

PCI_SPEED

DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the

PCI7510 device asserts this signal at a medium speed on nonconfiguration cycle accesses.

DATAPAR

RCU

Data parity error detected. This bit is set when the following conditions have been met:

a. PERR was asserted by any PCI device, including the PCI7510 device.

b. The PCI7510 device was the bus master during the data parity error.

c. The parity error response bit is set in the command register.

FBB_CAP

Fast back-to-back capable. The PCI7510 device cannot accept fast back-to-back transactions; thus,

this bit is hardwired to 0.

UDF

UDF supported. The PCI7510 device does not support the user definable features; thus, this bit is

hardwired to 0.

66MHZ

66-MHz capable. The PCI7510 device operates at a maximum PCLK frequency of 33 MHz;

therefore, this bit is hardwired to 0.

CAPLIST

Capabilities list. This bit returns 1 when read, indicating that the firmware loading function of the

PCI7510 device supports additional PCI capabilities.

INT_STATUS

Interrupt status. This bit reflects the interrupt status of the function. Since the firmware loader

function does not signal interrupts, this bit is hardwired to 0. This bit is disabled (read-only 0) if bit 0

(PCI2_3_EN) in the miscellaneous control register (see Section 11.24) is 0.

2–0

RSVD

Reserved. Bits 2–0 return 0s when read.

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